 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? L80227 10base-t/ 100base-tx ethernet phy technical manual october 2002
ii copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. thisdocumentcontainsproprietaryinformationoflsilogiccorporation.the informationcontainedhereinisnottobeusedbyordisclosedtothirdparties withouttheexpresswrittenpermissionofanof ? ceroflsilogiccorporation. db14-000139-02,thirdedition(october2002) thisdocumentdescribesrevision/release2oflsilogiccorporation s 10base-t/100base-txethernetphyandwillremaintheof ? cialreference sourceforallrevisions/releasesofthisproductuntilrescindedbyanupdate. lsilogiccorporationreservestherighttomakechangestoanyproductsherein atanytimewithoutnotice.lsilogicdoesnotassumeanyresponsibilityor liabilityarisingoutoftheapplicationoruseofanyproductdescribedherein, exceptasexpresslyagreedtoinwritingbylsilogic;nordoesthepurchaseor useofaproductfromlsilogicconveyalicenseunderanypatentrights, copyrights,trademarkrights,oranyotheroftheintellectualpropertyrightsoflsi logicorthirdparties. copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. trademarkacknowledgment lsilogicandthelsilogiclogodesignaretrademarksorregisteredtrademarks oflsilogiccorporation.allotherbrandandproductnamesmaybetrademarks oftheirrespectivecompanies. mt toreceiveproductliterature,visitusat http://www.lsilogic.com . foracurrentlistofourdistributors,salesof ? ces,anddesignresource centers,viewourwebpagelocatedat http://www.lsilogic.com/contacts/na_salesof ? ces.html L8022710base-t/100base-txethernetphytechnicalmanualiii copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. preface thisbookistheprimaryreferenceandtechnicalmanualfortheL80227 10base-t/100base-txethernetphysicallayerdevice(phy).it containsacompletefunctionaldescriptionforthedeviceandincludes completephysicalandelectricalspeci ? cationsfortheproduct. audience thisdocumentassumesthatyouhavesomefamiliaritywithethernet devicesandrelatedsupportdevices.thepeoplewhobene ? tfromthis bookare: engineersandmanagerswhoareevaluatingthedeviceforpossible useinasystem engineerswhoaredesigningthedeviceintoasystem organization thisdocumenthasthefollowingchapters: chapter1, introduction ,describesthedeviceingeneraltermsand givesablockdiagramandliststhedevicefeatures. chapter2, functionaldescription ,describeseachoftheinternal blocksinthedeviceinsomedetail. chapter3, signaldescriptions ,listsanddescribesthedeviceinput andoutputsignals. chapter4, registers ,givesaregistersummaryanddescribeseach ofthebitsineachregister. chapter5, managementinterface ,describesthedevice managementinterface,whichallowstheregisterstobereadand written. ivpreface copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. chapter6, speci ? cations ,liststheacanddccharacteristicsand givestypicaltimingparameters. appendixa, applicationinformation ,givespracticalguidelinesfor incorporatingthedeviceintoadesign. abbreviationsusedinthismanual belowisalistofabbreviationsusedthroughoutthismanual. 100base-t100mbit/stwisted-pairethernet 10base-t10mbit/stwisted-pairethernet 4b5b4-bit5-bit clkclock crccyclicredundancycheck crscarriersense csmacarriersensemultipleaccess cwrdcodeword dadestinationaddress eclemitter-coupledlogic eofendofframe esdendofstreamdelimiter fcsframechecksequence fdxfull-duplex feffarendfault fifofirstin-firstout flpfastlinkpulse fxfiber hdxhalf-duplex hizhighimpedance i/gindividual/group ietfinternetengineeringtaskforce ipginter-packetgap irefreferencecurrent l/tlengthandtype lsbleast-signi ? cantbit mibmanagementinformationbase mlt3multi-leveltransmission(3levels) msmillisecond msbmost-signi ? cantbit mvmillivolt nlpnormallinkpulse nrzinon-returntozeroinverted nrznon-returntozero opopcode pcbprintedcircuitboard pfpicofarad preface v copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. conventionsusedinthismanual the ? rsttimeawordorphraseisde ? nedinthismanual,itis italicized. theword assert meanstodriveasignaltrueoractive.theword deassert meanstodriveasignalfalseorinactive. hexadecimalnumbersareindicatedbythepre ? x 0x forexample, 0x32cf.binarynumbersareindicatedbythepre ? x 0b forexample, 0b0011.0010.1100.1111. prepreamble r/lhreadlatchedhigh r/lhireadlatchedhighwithinterrupt r/llreadlatchedlow r/llireadlatchedlowwithinterrupt r/ltreadlatchedtransition r/ltireadlatchedtransitionwithinterrupt r/wscread/writeselfclearing rfcrequestforcomments rj-45registeredjack-45 rmonremotemonitoring sastartaddressorstationaddress sfdstartofframedelimiter snmpsimplenetworkmanagementprotocol soistartofidle ssdstartofstreamdelimiter stpshieldedtwistedpair tptwistedpair hmicrohenry pmicroprocessor utpunshieldedtwistedpair vipreface copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. L8022710base-t/100base-txethernetphytechnicalmanualvii copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. contents chapter1 introduction 1.1overview1-1 1.2features1-3 chapter2 functionaldescription 2.1devicedifferences2-2 2.2overview2-3 2.2.1channeloperation2-3 2.2.2datapaths2-3 2.3blockdiagramdescription2-8 2.3.1oscillatorandclock2-8 2.3.2controllerinterface2-9 2.3.3encoder2-12 2.3.4decoder2-13 2.3.5scrambler2-14 2.3.6descrambler2-14 2.3.7twisted-pairtransmitters2-15 2.3.8twisted-pairreceiver2-18 2.3.9clockanddatarecovery2-21 2.3.10linkintegrityandautonegotiation2-22 2.3.11linkindication2-26 2.3.12collision2-26 2.3.13leddrivers2-28 2.4startofpacket2-30 2.4.1100mbits/s2-30 2.4.210mbits/s2-31 2.5endofpacket2-31 viiicontents copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.5.1100mbits/s2-32 2.5.210mbits/s2-32 2.6full-/half-duplexmode2-33 2.6.1forcingfull-/half-duplexoperation2-34 2.6.2full/halfduplexindication2-34 2.6.3loopback2-34 2.710/100mbits/sselection2-35 2.7.1forcing10/100mbits/soperation2-35 2.7.2autoselecting10/100mbits/soperation2-35 2.7.310/100mbits/sindication2-36 2.8jabber2-36 2.9reset2-36 2.10receivepolaritycorrection2-37 chapter3 signaldescriptions 3.1mediainterfacesignals3-2 3.2controllerinterfacesignals(mii)3-3 3.3managementinterface(mi)/ledsignals3-4 3.4ledsignals3-6 3.5miscellaneoussignals3-7 3.6powersupply3-8 chapter4 registers 4.1bittypes4-1 4.2miserialportregistersummary4-3 4.3registers4-5 4.3.1controlregister(register0)4-5 4.3.2statusregister(register1)4-7 4.3.3phyid1register(register2)4-9 4.3.4phyid2register(register3)4-10 4.3.5autonegotiationadvertisementregister (register4)4-11 4.3.6autonegotiationremoteendcapabilityregister (register5)4-13 4.3.7con ? gurationregister(register17)4-15 contentsix copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.3.8channelstatusoutput0register(register18)4-17 chapter5 managementinterface 5.1signaldescription5-1 5.2generaloperation5-2 5.3framestructure5-4 5.4registerstructure5-5 chapter6 speci ? cations 6.1absolutemaximumratings6-1 6.2electricalcharacteristics6-2 6.2.1twisted-pairdccharacteristics6-3 6.3acelectricalcharacteristics6-6 6.3.125mhzinput/outputclocktimingcharacteristics6-7 6.3.2transmittimingcharacteristics6-7 6.3.3receivetimingcharacteristics6-11 6.3.4collisionandjamtimingcharacteristics6-16 6.3.5linkpulsetimingcharacteristics6-19 6.3.6jabbertimingcharacteristics6-25 6.3.7miserialporttimingcharacteristics6-26 6.4pinoutsandpackagedrawings6-27 6.4.1L80227pinouts6-27 6.4.2L80227pinlayout6-33 6.5mechanicaldrawing6-34 appendixa applicationinformation a.1exampleschematicsa-1 a.2tptransmitinterfacea-5 a.3tpreceiveinterfacea-6 a.4tptransmitoutputcurrentseta-7 a.5transmitterdroopa-8 a.6miicontrollerinterfacea-8 a.6.1clocksa-8 a.6.2outputdrivea-9 xcontents copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. a.6.3miidisablea-10 a.6.4receiveoutputenablea-11 a.7repeaterapplicationsa-11 a.7.1miibasedrepeatersa-11 a.7.2clocksa-11 a.8serialporta-12 a.8.1serialportaddressinga-12 a.9oscillatora-14 a.10leddriversa-15 a.11powersupplydecouplinga-15 customerfeedback xi copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figures 1.1toplevelblockdiagram1-2 2.1L80227deviceblockdiagram2-4 2.2100base-txand10base-tframeformat2-5 2.3miiframeformat2-6 2.4tpoutputvoltagetemplate2-17 2.5tpinputvoltagetemplate(10mbits/s)2-19 2.6linkpulseoutputvoltagetemplate(10mbits/s)2-23 2.7nlpvsflplinkpulse2-24 2.8soioutputvoltagetemplate(10mbits/s)2-33 3.1devicelogicdiagram3-2 5.1miserialportframetimingdiagram5-3 5.2miserialframestructure5-4 6.125mhzoutputtiming6-7 6.2transmittiming(100mbits/s)6-9 6.3transmittiming(10mbits/s)6-10 6.4receivetiming,startofpacket(100mbits/s)6-13 6.5receivetiming,endofpacket(100mbits/s)6-13 6.6receivetiming,startofpacket(10mbits/s)6-14 6.7receivetiming,endofpacket(10mbits/s)6-15 6.8rx_entiming6-15 6.9collisiontiming,receive(100mbits/s)6-17 6.10collisiontiming,receive(10mbits/s)6-17 6.11collisiontiming,transmit(100mbits/s)6-18 6.12collisiontiming,transmit(10mbits/s)6-18 6.13collisiontesttiming6-18 6.14nlplinkpulsetiming6-23 6.15flplinkpulsetiming6-24 6.16jabbertiming6-25 6.17miserialporttiming6-26 6.18L8022764-pinlqfp,topview6-33 6.1964-pinlqfppackagedrawing6-34 a.1typicalnetworkinterfaceadaptercardschematicusing theL80227a-2 a.2typicalswitchingportschematicusingL80227a-3 a.3typicalexternalphyschematicusingL80227a-4 a.4miioutputdrivercharacteristicsa-10 xii copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. a.5serialdeviceportaddressselectiona-13 a.6connectingtheL80227toahigh-capacitancecrystala-14 a.7connectingtheL80227toanonhigh-capacitancecrystala-14 xiii copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. tables 2.1devicedifferences2-2 2.2transmitpreambleandsfdbitsatmacnibbleinterface2-6 2.3receivepreambleandsfdbitsatmacnibbleinterface2-7 2.44b/5bsymbolmapping2-10 2.5tpoutputvoltage(10mbits/s)2-17 2.6pledn_[1:0]outputselectbitencoding2-29 2.7lednormalfunctionde ? nition2-29 2.8ledeventde ? nition2-30 4.1miregisterbittypede ? nition4-2 5.1miserialportregistersummary5-6 6.1absolutemaximumratings6-1 6.2dccharacteristics6-2 6.3twistedpaircharacteristics(transmit)6-4 6.4twistedpaircharacteristics(receive)6-5 6.5testconditions6-6 6.625mhzinput/outputclock6-7 6.7transmittiming6-8 6.8receivetiming6-11 6.9collisionandjamtiming6-16 6.10linkpulsetiming6-19 6.11jabbertiming6-25 6.12miserialporttiming6-26 6.13L80227pinlist(bysignalcategory)6-27 6.14L80227pinlist(bypinnumber)6-30 a.1tptransformerspeci ? cationa-5 a.2tptransformersourcesa-5 a.3nonhigh-capacitancecrystalspeci ? cationsa-15 xiv copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. L8022710base-t/100base-txethernetphytechnicalmanual1-1 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. chapter1 introduction thischaptercontainsabriefintroductiontotheL8022710base- t/100base-txethernetphysicallayerdevice(phy).itcontainsthe followingsections: section1.1, overview section1.2, features 1.1overview thismanualdescribestheL80227device.thedevicecontainsasingle phychannel.theconventionusedinthismanualisthat device refers totheic,and channel referstothephyinthedevice. theL80227isahighly-integratedanaloginterfaceicfortwisted-pair ethernetapplicationsandcanbecon ? guredforeither100mbits/s (100base-tx)or10mbits/s(10base-t)ethernetoperation. thephychannelcontainsthefollowingblocks: 4b5bencoder/manchesterencoder scrambler 10base-ttransmitter 100base-txtransmitter 10base-treceiver 100base-txreceiver squelch clockanddatarecovery linkintegrityandautonegotiation 1-2introduction copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. descrambler 4b5bdecoder/manchesterdecoder miicontrollerinterface managementinterface(mi) collisiondetection figure1.1 isasimpli ? edtop-levelblockdiagramoftheL80227device. figure1.1toplevelblockdiagram internaloutputwaveshapingcircuitryandon-chip ? ltersinthephy eliminatestheneedforexternal ? ltersnormallyrequiredin100base-tx and10base-tapplications. oscin interface serial controller collision 4b5b encoder scrambler 4b5b decoder descrambler clock & data recovery auto- and link negotiation recovery clock & data (manchester decoder) manchester encoder oscillator led drivers port (mi) squelch squelch (mii) controller ethernet leds 100base-tx transmitter 10base-t transmitter 100base-tx receiver 10base-t receiver L80227 tp interface features1-3 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. usingtheon-chipautonegotiationalgorithm,thedevicecan automaticallycon ? gurethephychanneltoindependentlyoperatein 100mbits/sor10mbits/soperationineitherfull-orhalf-duplexmode. thedeviceusesthemanagementinterface(mi)serialporttoaccess eight16-bitregistersinthephy.theseregisterscomplytoclause22of ieee802.3uandcontainbitsand ? eldsthatre ? ectcon ? gurationinputs, statusoutputs,anddevicecapabilities. thedeviceisideallysuitedasamediainterfacefor 10base-t/100base-txrepeaters,routers,pcmciacards,niccards, networkedmodems,andotherendstationapplications. thedeviceisimplementedineither0.35or0.30microncmos technologyandoperatesona3.3vpowersupply. 1.2features thefollowinglistsummarizesthesalientfeaturesofthedevices: single-chipsolutionfora10base-t/100base-txphy dualspeed:10/100mbit/s half-duplexorfull-duplexoperation miiinterfacetoethernetmac managementinterface(mi)forcon ? gurationandstatus autonegotiationfor10/100mbit/s,full/halfduplexoperation autonegotiationadvertisementcontrolthroughpins allapplicableieee802.3,10base-tand100base-tx speci ? cationsaremet on-chipwaveshaping(noexternal ? ltersrequired) adaptiveequalizerfor100base-txoperation baselinewandercorrection minimumnumberofexternalcomponents ledsareindividuallyprogrammabletore ? ectanythefollowing events: C link 1-4introduction copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. C activity C collision C full-duplex C 10/100mbits/s 3.3vpowersupply,5vtoleranti/o 64-pinlqfp operatingtemperaturerangesavailable: C commercial(L80227):0 ? to+70 ? c C industrial(L80227i):-40 ? to+85 ? c L8022710base-t/100base-txethernetphytechnicalmanual2-1 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. chapter2 functionaldescription thischaptercontainsafunctionaldescriptionofthephydevice.ithas thefollowingsections: section2.1, devicedifferences section2.2, overview section2.3, blockdiagramdescription section2.4, startofpacket section2.5, endofpacket section2.6, full-/half-duplexmode section2.7, 10/100mbits/sselection section2.8, jabber section2.9, reset section2.10, receivepolaritycorrection 2-2functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.1devicedifferences thismanualdescribestheL80227phy.itissimilartothel80223and l80225phydevices.eachofthesedevicesissimilarwithrespectto ethernetoperation. table2.1 showsthesimilaritiesanddifferencesinthe devices. table2.1devicedifferences functionl80223l80225L80227 powersupply3.3v3.3v3.3v resetpinyesyesyes fxinterfaceyesnono transmittransformerwindingratio1:11:11:1 speedpinyesyesyes duplexpinyesyesyes hardwareadvertisementcontrolnoyesno registers16 C 20yes#18#17,#18 availableinindustrialtemperature range nonoyes overview2-3 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.2overview thissectiongivesabriefoverviewofthedevicefunctionaloperation. theL80227isacomplete100/10mbits/sethernetmediainterfaceic.a blockdiagramisshownin figure2.1 . note:unlessotherwisenoted,theoperationandspeci ? cations fortheindustrialtemperaturedevicesareidenticaltothe commercialtemperaturerangedevice. 2.2.1channeloperation thephyoperatesinthe100base-txmodeat100mbits/smode,orin the10base-tmodeat10mbits/s.the100mbits/smodeandthe 10mbits/smodedifferindatarate,signalingprotocol,andallowedwiring asfollows: 100base-txmodeusestwopairsofcategory5orbetterutpor stptwisted-paircablewith4b5bencoded,scrambled,andmlt3 coded62.5mhzternarydatatoachieveathroughputof100mbits/s. 10mbits/smodeusestwopairsofcategory3orbetterutporstp twisted-paircablewithmanchesterencoded10mhzbinarydatato achievea10mbits/sthroughput thedatasymbolformatonthetwisted-paircableforthe100and10 mbits/smodesisde ? nedinieee802.3speci ? cationsandshownin figure2.2 . 2.2.2datapaths ineachdevice,thereisatransmitdatapathandareceivedatapath associatedwitheachphychannel.thetransmitdatapathisfromthe controllerinterfacetothetwisted-pairtransmitter.thereceivedatapath isfromthetwisted-pairreceivertothecontrollerinterface. 2-4functionaldescription rev.bcopyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. f i g u r e 2 . 1 l 8 0 2 2 7 d e v i c e b l o c k d i a g r a m overview2-5 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure2.2100base-txand10base-tframeformat interframe gap preamble sfd da sa ln llc data fcs interframe gap ethernet mac frame ssd da sa ln llc datafcs 100 base-tx data symbols idle preamble sfd esdidle idle = ssd = preamble = sfd = da, sa, ln, llc data, fcs = esd = [ 1 1 1 1 ...] [ 1 1 0 0 0 1 0 0 0 1 ] [ 1 0 1 0 ...] 62 bits long [ 1 1 ] [ data ] [ 0 1 1 0 1 0 0 1 1 1 ] before/after 4b5bencoding, scrambling,and mlt3coding da sa ln llc datafcs 10 base-t data symbols idlepreamble sfd soiidle idle = preamble = sfd = da, sa, ln, llc data, fcs = [ notransitions ] [ 1 1 ] [ data ] [ 1 1 ] with no mid bit soi = transition [ 1 0 1 0 ...] 62 bits long before/after manchester encoding 2-6functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.2.2.1100base-txoperation in100base-txtransmitoperation,dataisreceivedonthecontroller interfacefromanexternalethernetcontrolleraccordingtotheformat shownin figure2.3 and table2.2 .thedataissenttothe4b5bencoder, whichscramblestheencodeddata.thescrambleddataisthensentto thetptransmitter.thetptransmitterconvertstheencodedand scrambleddataintomlt3ternaryformat,preshapestheoutput,and drivesthetwisted-paircable. figure2.3miiframeformat table2.2transmitpreambleandsfdbitsatmacnibbleinterface signalsbitvalue txdoxx1 1 1.1stpreamblenibbletransmitted. 11111111111111 2 2.1stsfdnibbletransmitted. 1d0 3 3.1stdatanibbletransmitted. d4 4 4.d0throughd7arethe ? rst8bitsofthedata ? eld. txd1xx0000000000000000d1d5 txd2xx1111111111111111d2d6 txd3xx0000000000000001d3d7 tx_en00111111111111111111 prmble sfd data 1 tx_en = 1 preamble = sfd = datan = idle = [ 1 0 1 0 ...] 62 bits long [ 1 1 ] [between 64 1518 data bytes] tx_en = 0 tx_en = 0 idle preamble start of frame data nibbles data 2 data n-1 data n 62 bits2 bits a. mii frame format b. mii nibble order d0 d1 d2 d3d4 first bit mac serial bit stream d5 d6 d7 lsb txd2/rxd2 txd3/rxd3 tx_en = 0 idle msb second nibble txd0/rxd0 txd1/rxd1 first nibble mii nibble stream overview2-7 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. in100base-txreceiveoperation,thetpreceivertakesincoming encodedandscrambledmlt3datafromthetwisted-paircable,removes anyhigh-frequencynoisefromtheinput,equalizestheinputsignalto compensatefortheeffectsofthecable,performsbaselinewander correction,quali ? esthedatawithasquelchalgorithm,andconvertsthe datafrommlt3-encodedlevelstointernaldigitallevels.theoutputofthe receiverthengoestoaclockanddatarecoveryblockthatrecoversa clockfromtheincomingdata,usestheclocktolatchvaliddataintothe device,andconvertsthedatabacktonrzformat.the4b5bdecoder anddescramblerthendecodesanddescramblesthenrzdata, respectively,andsendsitoutofthecontrollerinterfacetoanexternal ethernetcontroller.theformatofthereceiveddataatthecontroller interfaceisasshownin table2.3 . 2.2.2.210base-toperation 10base-toperationissimilartothe100base-txoperationexcept thereisnoscrambler/descrambler theencoder/decoderismanchesterinsteadof4b5b thedatarateis10mbits/sinsteadof100mbits/s, thetwisted-pairsymboldataistwo-levelmanchesterinsteadof ternarymlt-3. thetransmittergenerateslinkpulsesduringtheidleperiod thetransmitterdetectsthejabbercondition thereceiverdetectslinkpulsesandimplementstheautonegotiation algorithm table2.3receivepreambleandsfdbitsatmacnibbleinterface signalsbitvalue rxdox1 1 111111111111111 2 1d0 3 d4 4 rxd1x00000000000000000d1d5 rxd2x11111111111111111d2d6 rxd3x00000000000000001d3d7 rx_dv01111111111111111111 1.firstpreamblenibblereceived.dependingonthemode,thedevicemayeliminateeitherallorsome ofthepreamblenibbles,uptothe ? rstsfdnibble. 2.firstsfdnibblereceived. 3.firstdatanibblereceived. 4.d0throughd7arethe ? rst8bitsofthedata ? eld. 2-8functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3blockdiagramdescription theL80227phydevicehasthefollowingmainblocks: oscillatorandclock controllerinterface 4b5b/manchesterencoder/decoder scrambler/descrambler twisted-pairtransmitter twisted-pairreceiver clockanddatarecovery linkintegrity/autonegotiation descrambler linkindication collisiondetection leddrivers amanagementinterface(mi)serialportprovidesaccesstoeightinternal phyregisters. figure2.1 showsthemainblocks,alongwiththeirassociatedsignals. thefollowingsectionsdescribeeachoftheblocksin figure2.1 .the performanceofthedeviceinboththe10and100mbits/smodesis described. 2.3.1oscillatorandclock theL80227requiresa25mhzreferencefrequencyforinternalsignal generation.this25mhzreferencefrequencyisgeneratedwitheitheran external25mhzcrystalconnectedbetweenoscinandgndorwiththe applicationofanexternal25mhzclocktooscin. thedeviceprovideseithera2.5mhzor25mhzreferenceclockatthe tx_clkorrx_clkoutputpinsfor10-mhzor100mhzoperation, respectively. blockdiagramdescription2-9 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3.2controllerinterface thissectiondescribesthecontrollerinterfaceoperation. 2.3.2.1highimpedancecontrol whentherx_enpinislow,thefollowingcontrollerinterfaceoutputs areplacedinthehighimpedancestate: rx_clk rxd[3:0] rx_dv rx_er col 2.3.2.2miiinterface thedevicehasanmiiinterfacetoanexternalethernetmediaaccess controller(mac). mii(100mbits/s) C themiiisanibble-widepacketdatainterface de ? nedinieee802.3andshownin figure2.3 .theL80227meetsall themiirequirementsoutlinedinieee802.3.theL80227candirectly connect,withoutanyexternallogic,toanyethernetcontrollerorother devicethatalsocomplieswiththeieee802.3miispeci ? cations. themiiinterfacecontainsthefollowingsignals: transmitdatabits(txd[3:0]) transmitclock(tx_clk) transmitenable(tx_en) transmiterror(tx_er) receivedatabits(rxd[3:0]) receiveclock(rx_clk) carriersense(crs) receivedatavalid(rx_dv) receivedataerror(rx_er) collision(col). 2-10functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. thetransmitandreceiveclocksoperateat25mhzin100mbits/smode. onthetransmitside,thetx_clkoutputrunscontinuouslyat25mhz. whennodataistobetransmitted,tx_enmustbedeasserted.while tx_enisdeasserted,tx_erandtxd[3:0]areignoredandnodatais clockedintothedevice.whentx_enisassertedontherisingedgeof tx_clk,dataontxd[3:0]isclockedintothedeviceontherisingedge ofthetx_clkoutputclock.txd[3:0]inputdataisnibble-widepacket datawhoseformatmustbethesameasspeci ? edinieee802.3and shownin figure2.3 .whenalldataontxd[3:0]hasbeenlatchedinto thedevice,tx_enmustbedeassertedontherisingedgeoftx_clk. tx_erisalsoclockedinontherisingedgeoftx_clk.tx_erisa transmiterrorsignal.whenthissignalisasserted,thedevicesubstitutes anerrornibbleinplaceofthenormaldatanibblethatwasclockedinon txd[3:0].theerrornibbleisde ? nedtobethe/h/symbol,whichis de ? nedinieee802.3andshownin table2.4 . table2.44b/5bsymbolmapping symbolnamedescription5bcode4bcode 0data00b111100b0000 1data10b010010b0001 2data20b101000b0010 3data30b101010b0011 4data40b010100b0100 5data50b010110b0101 6data60b011100b0110 7data70b011110b0111 8data80b100100b1000 9data90b100110b1001 adataa0b101100b1010 bdatab0b101110b1011 cdatac0b110100b1100 ddatad0b110110b1101 blockdiagramdescription2-11 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. becausetheoscininputclockgeneratesthetx_clkoutputclock,the txd[3:0],tx_en,andtx_ersignalsarealsoclockedinonrising edgesofoscin. onthereceiveside,aslongasavaliddatapacketisnotdetected,crs andrx_dvaredeassertedandtherxd[3:0]signalsareheldlow. whenthestartofpacketisdetected,crsandrx_dvareassertedon thefallingedgeofrx_clk.theassertionofrx_dvindicatesthatvalid dataisclockedoutonrxd[3:0]onthefallingedgeoftherx_clk.the rxd[3:0]datahasthesameframestructureasthetxd[3:0]dataand isspeci ? edinieee802.3andshownin figure2.3 .whentheendofthe packetisdetected,crsandrx_dvaredeasserted,andrxd[3:0]is heldlow.crsandrx_dvalsostaydeassertedifthedeviceisinthe linkfailstate. rx_erisareceiveerroroutputthatisassertedwhencertainerrorsare detectedonadatanibble.rx_erisassertedonthefallingedgeof rx_clkforthedurationofthatrx_clkclockcycleduringwhichthe nibblecontainingtheerrorisoutputonrxd[3:0]. thecollisionoutput,col,isassertedwheneverthecollisionconditionis detected. edatae0b111000b1110 fdataf0b111010b1111 iidle0b111110b0000 jssd#10b110000b0101 kssd#20b100010b0101 tesd#10b011010b0000 resd#20b001110b0000 hhalt0b00100unde ? ned C invalidcodesallothers 1 0b0000* 1.these5bcodesarenotused.thedecoderdecodesthese5bcodesto 4b0000.theencoderencodes4b0000to5b11110,asshowninsymbol data0. table2.44b/5bsymbolmapping(cont.) symbolnamedescription5bcode4bcode 2-12functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. mii(10mbits/s) C mii10mbits/soperationisidenticalto100mbits/s operationexcept tx_clkandrx_clkclockfrequencyisreducedto2.5mhz tx_erisignored rx_erisdisabledandalwaysheldlow receiveoperationismodi ? edasfollows: onthereceiveside,whenthesquelchcircuitdeterminesthatinvalid dataispresentonthetpinputs,thereceiverisidle.duringidle, rx_clkfollowstx_clk,rxd[3:0]isheldlow,andcrsand rx_dvaredeasserted.whenastartofpacketisdetectedonthe tpreceiveinputs,crsisassertedandtheclockrecoveryprocess startsontheincomingtpinputdata.afterthereceiveclockis recoveredfromthedata,therx_clkisswitchedovertothe recoveredclockandthedatavalidsignalrx_dvisassertedona fallingedgeofrx_clk.oncerx_dvisasserted,validdatais clockedoutonrxd[3:0]onthefallingedgeofrx_clk.the rxd[3:0]datahasthesamepacketstructureasthetxd[3:0]data andisformattedonrxd[3:0]asspeci ? edinieee802.3andshown in figure2.3 .whentheendofpacketisdetected,crsandrx_dv aredeasserted.crsandrx_dvalsostaydeassertedaslongas thedeviceisinthelinkfailstate. miidisable C todisablethemiiinputsandoutputs,setthemii_disbit inthemiserialportcontrolregister.whenthemiiisdisabled,themii inputsareignored,andthemiiandtpoutputsareplacedinahigh- impedancestate. ifthemiaddresslines,mda[3:0]n,arepulledhighduringresetor powerup,theL80227powersupandresetswiththemiidisabled. otherwise,theL80227powersupandresetswiththemiienabled. 2.3.3encoder thissectiondescribesthe4b5bencoder,whichisusedin100mbits/s operation.italsodescribesthemanchesterencoder,usedin10base-t operation. blockdiagramdescription2-13 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3.3.14b5bencoder(100mbits/s) 100base-txoperationrequiresthatthedatabe4b5bencoded.the 4b5bencoderblockshownin figure2.1 convertsthefour-bitdata nibblesinto ? ve-bitdatawords.themappingofthe4bnibblesto5b codewordsisspeci ? edinieee802.3andisshownin table2.4 . the4b5bencodertakes4b(four-bit)nibblesfromthetransmitmac block,convertstheminto5b( ? ve-bit)wordsaccordingto table2.4 ,and sendsthe5bwordstothescrambler.the4b5bencoderalsosubstitutes the ? rsteightbitsofthepreamblewiththestartofstreamdelimiter (ssd)(/j/k/symbols)andaddsanendofstreamdelimiter(esd)(/t/r/ symbols)totheendofeachpacket,asde ? nedinieee802.3andshown in figure2.2 .the4b5bencoderalso ? llstheperiodbetweenpackets (idleperiod),withacontinuousstreamofidlesymbols,asshownin figure2.2 . 2.3.3.2manchesterencoder(10mbits/s) themanchesterencodershownin figure2.1 isusedfor10mbits/s operation.itcombinesclockandnon-returntozeroinverted(nrzi)data suchthatthe ? rsthalfofthedatabitcontainsthecomplementofthe data,andthesecondhalfofthedatabitcontainsthetruedata,as speci ? edinieee802.3.thisprocessguaranteesthatatransitionalways occursinthemiddleofthebitcell.themanchesterencoderonthe deviceconvertsthe10mbits/snrzidatafromtheethernetcontroller interfaceintoasingledatastreamforthetptransmitterandaddsastart ofidlepulse(soi)attheendofthepacketasspeci ? edinieee802.3 andshownin figure2.2 .themanchesterencodingprocessisonlydone onactualpacketdata;duringtheidleperiodbetweenpackets,nosignal istransmittedexceptforperiodiclinkpulses. 2.3.4decoder thissectiondescribesthe4b5bdecoder,usedin100mbits/soperation, whichconverts5bencodeddatato4bnibbles.italsodescribesthe manchesterdecoder,usedin10base-toperation. 2.3.4.14b5bdecoder(100mbits/s) becausethetpinputdatais4b5bencodedonthetransmitside,the 4b5bdecodermustdecodeitonthereceiveside.themappingofthe 2-14functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 5bcodewordstothe4bnibblesisspeci ? edinieee802.3.the4b5b decodertakesthe5bcodewordsfromthedescrambler,convertsthem into4bnibblesaccordingto table2.4 ,andsendsthe4bnibblestothe receiveethernetcontroller. the4b5bdecoderalsostripsoffthessddelimiter(/j/k/symbols),and replacesitwithtwo4bdata5nibbles(/5/symbol).italsostripsoffthe esddelimiter(/t/r/symbols),andreplacesitwithtwo4bdata0nibbles (/i/symbol),perieee802.3speci ? cations(see figure2.2 ). the4b5bdecoderdetectsssd,esd,andcodeworderrorsinthe incomingdatastreamasspeci ? edinieee802.3.toindicatethese errors,thedeviceassertstherx_eroutputwhiletheerrorsarebeing transmittedacrossrxd[3:0]. 2.3.4.2manchesterdecoder(10mbits/s) inmanchestercodeddata,the ? rsthalfofthedatabitcontainsthe complementofthedata,andthesecondhalfofthedatabitcontainsthe truedata.themanchesterdecoderconvertsthesingledatastreamfrom thetpreceiverintonon-returntozero(nrz)dataforthecontroller interface.todothis,itdecodesthedataandstripsoffthesoipulse. becausetheclockanddatarecoveryblockhasalreadyseparatedthe clockanddatafromthetpreceiver,thatblockinherentlyperformsthe themanchesterdecoding. 2.3.5scrambler 100base-txtransmissionrequiresscramblingtoreducetheradiated emissionsonthetwistedpair.thescramblertakesthenrziencoded datafromthe4b5bencoder,scramblesitpertheieee802.3 speci ? cations,andsendsittothetptransmitter.ascramblerisnotused for10mbits/soperation. 2.3.6descrambler thedescramblerblockshownin figure2.1 isusedin 100base-txoperation.thedevicedescramblertakesthescrambled nrzidatafromthedatarecoveryblock,descramblesitaccordingto ieee802.3speci ? cations,alignsthedataonthecorrect5bword boundaries,andsendsittothe4b5bdecoder. blockdiagramdescription2-15 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. thealgorithmforsynchronizationofthedescrambleristhesameasthe algorithmoutlinedintheieee802.3speci ? cation. afterthedescramblerissynchronized,itmaintainssynchronizationas longasenoughdescrambledidlepatternonesaredetectedwithina giveninterval.tostayinsynchronization,thedescramblerneedsto detectatleast25consecutivedescrambledidlepatternonesina1ms interval.if25consecutivedescrambledidlepatternonesarenot detectedwithinthe1msinterval,thedescramblergoesoutof synchronizationandrestartsthesynchronizationprocess. thedescramblerisdisabledfor10base-toperation. 2.3.7twisted-pairtransmitters thissectiondescribestheoperationofthe10and100mbits/stp transmitters. 2.3.7.1100mbits/stptransmitter thetptransmitterconsistsofanmlt3encoder,waveformgenerator, andlinedriver. themlt3encoderconvertsthenrzidatafromthescramblerintoa three-levelcoderequiredbyieee802.3.mlt3codingusesthreelevels, convertingonestotransitionsbetweenthethreelevels,andzerostono transitionsorchangesinlevel. thepurposeofthewaveformgeneratoristoshapethetransmitoutput pulse.thewaveformgeneratortakesthemlt3three-levelencoded waveformandusesanarrayofswitchedcurrentsourcestocontrolthe shapeofthetwisted-pairoutputsignal.thewaveformgeneratorconsists ofswitchedcurrentsources,aclockgenerator, ? lter,andlogic.the switchedcurrentsourcescontroltheriseandfalltimeaswellassignal leveltomeetieee802.3requirements.theoutputoftheswitched currentsourcesgoesthroughasecondorderlow-pass ? lterthat smooths thecurrentoutputandremovesanyhigh-frequency components.inthisway,thewaveformgeneratorpreshapestheoutput waveformtransmittedontothetwisted-paircablesuchthatthewaveform meetsthepulsetemplaterequirementsoutlinedinieee802.3.the waveformgeneratoreliminatestheneedforanyexternal ? ltersonthetp transmitoutput. 2-16functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. thelinedriverconvertstheshapedandsmoothedwaveformtoacurrent outputthatcandrivegreaterthan100metersofcategory5unshielded twisted-paircableor150-ohmshieldedtwisted-paircable. 2.3.7.210mbits/stptransmitter eventhoughthe10mbits/stransmitteroperationismuchdifferentthan thatof100mbits/s,italsoconsistsofawaveformgeneratorandline driver(see figure2.1 ). thewaveformgenerator,whichconsistsofarom,dac,clock generator,and ? lter,shapestheoutputtransmitpulse.thedac generatesastair-steppedrepresentationofthedesiredoutputwaveform. thestair-steppeddacoutputthenispassedthroughalow-pass ? lterto smooth thedacoutputandremoveanyhigh-frequencycomponents. thedacvaluesaredeterminedfromthedataattheromaddresses. thedataischosentoshapethepulsetothedesiredtemplate.theclock generatorclocksthedataintothedacathighspeed.inthisway,the waveformgeneratorpreshapestheoutputwaveformtobetransmitted ontothetwisted-paircabletomeetthepulsetemplaterequirements outlinedinieee802.3clause14andshownin figure2.4 .the waveshaperreplacesandeliminatesexternal ? ltersonthetptransmit output. thelinedriverconvertstheshapedandsmoothedwaveformtoacurrent outputthatcandrivegreaterthan100metersofcategory3/4/5100-ohm unshieldedtwisted-paircableor150-ohmshieldedtwisted-paircable withoutanyexternal ? lters. duringtheidleperiod,nooutputsignalsaretransmittedonthetp outputsexceptforlinkpulses. blockdiagramdescription2-17 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure2.4tpoutputvoltagetemplate t 1.0 0.8 0.6 0.4 0.2 0.0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 0102030405060708090100110 time (ns) voltage (v) a b c d e g n o p q t v w u r s l k j m i h f table2.5tpoutputvoltage(10mbits/s) referencetime(ns)internalmauvoltage(v) a00 b151.0 c150.4 d250.55 e320.45 f420 g57 1.0 h480.7 i670.6 j920 k74 0.55 l73 0.55 2-18functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3.8twisted-pairreceiver thedeviceiscapableofoperatingateither10-or100-mbits/s.this sectiondescribesthetwisted-pairreceiversandsquelchoperationfor bothmodesofoperation. 2.3.8.1100mbits/stpreceiver thetpreceiverdetectsinputsignalsfromthetwisted-pairinputand convertsthemtoadigitaldatabitstreamreadyforclockanddata recovery.thereceivercanreliablydetect100base-txcompliant transmitterdatathathasbeenpassedthrough0to100metersof 100-ohmcategory5utpor150-ohmstpcable. the100mbits/sreceiverconsistsofanadaptiveequalizer,baseline wandercorrectioncircuit,comparators,andanmlt3decoder.thetp inputs ? rstgotoanadaptiveequalizer.theadaptiveequalizer compensatesforthelow-passcharacteristicsofthecableandcanadapt andcompensatefor0to100metersofcategory5,100-ohmor150-ohm stpcable.thebaselinewandercorrectioncircuitrestoresthedc componentoftheinputwaveformthattheexternaltransformershave removed.thecomparatorsconverttheequalizedsignalbacktodigital levelsandqualifythedatawiththesquelchcircuit.themlt3decoder m580 n851.0 o1000.4 p1100.75 q1110.15 r1080 s111 0.15 t110 1.0 u100 0.3 v110 0.7 w90 0.7 table2.5tpoutputvoltage(10mbits/s)(cont.) referencetime(ns)internalmauvoltage(v) blockdiagramdescription2-19 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. takesthethree-levelmlt3encodedoutputdatafromthecomparators andconvertsittonormaldigitaldatatobeusedforclockanddata recovery. 2.3.8.210mbits/stpreceiver the10mbits/sreceiverdetectsinputsignalsfromthetwisted-paircable thatarewithinthetemplateshownin figure2.5 .thetpinputsare biasedbyinternalresistorsandgothroughalow-pass ? lterdesignedto eliminateanyhigh-frequencyinputnoise.theoutputofthereceive ? lter goestotwodifferenttypesofcomparators:squelchandzerocrossing. thesquelchcomparatordetermineswhetherthesignalisvalid,andthe zero-crossingcomparatorsensestheactualdatatransitionsafterthe signalisdeterminedtobevalid.theoutputofthesquelchcomparator goestothesquelchcircuitandisalsousedforlinkpulsedetection,soi detection,andreversepolaritydetection.theoutputofthezero-crossing comparatorisusedforclockanddatarecoveryinthemanchester decoder. figure2.5tpinputvoltagetemplate(10mbits/s) short bit 585 mv sin ( t/pw) 0pw 585 mv 3.1 v slope 0.5 v/ns 585 mv 3.1 v long bit 585 mv sin[2 (t pw2)/pw)] 585 mv sin ( t/pw) slope 0.5 v/ns 0pw/43pw/4pw 2-20functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3.8.3squelch(100mbits/s) thesquelchblockdeterminesifthetpinputcontainsvaliddata.the 100mbits/stpsquelchisoneofthecriteriausedtodeterminelink integrity.thesquelchcomparatorscomparethetpinputsagainst ? xed positiveandnegativethresholdscalledsquelchlevels.theoutputfrom thesquelchcomparatorgoestoadigitalsquelchcircuit,which determineswhetherthereceiveinputdataonthatportisvalid.ifthedata isinvalid,thereceiverisinthesquelchedstate.iftheinputvoltage exceedsthesquelchlevelsatleastfourtimeswithalternatingpolarity withina10 sinterval,thesquelchcircuitdeterminesthatthedatais validandthereceiverentersintotheunsquelchstate. intheunsquelchstate,thereceivethresholdlevelisreducedby approximately30%fornoiseimmunityreasonsandiscalledthe unsquelchlevel.whenthereceiverisintheunsquelchstate,theinput signalisconsideredvalid. thedevicestaysintheunsquelchstateuntillossofdataisdetected. lossofdataisdetectedifnoalternatingpolarityunsquelchtransitions aredetectedduringany10 sinterval.whenalossofdataisdetected, thereceivesquelchisturnedonagain. 2.3.8.4squelch(10mbits/s) thetpsquelchalgorithmfor10mbits/smodeisidenticaltothe 100mbits/smode,except the10mbits/stpsquelchalgorithmisnotusedforlinkintegrity,but tosensethebeginningofapacket thereceivergoesintotheunsquelchstateiftheinputvoltage exceedsthesquelchlevelsforthreebittimeswithalternatingpolarity withina50to250nsinterval thereceivergoesintothesquelchstatewhensoiisdetected unsquelchdetectionhasnoeffectonlinkintegrity(linkpulsesare usedin10mbits/smodeforthatpurpose) startofpacketisdeterminedwhenthereceivergoesintothe unsquelchstateandcrsisasserted thereceivermeetsthesquelchrequirementsde ? nedinieee802.3 clause14. blockdiagramdescription2-21 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3.9clockanddatarecovery thissectiondescribesclockanddatarecoverymethodsimplementedin thedeviceforboththe100mbits/sand10mbits/smodes. 2.3.9.1100mbits/sclockanddatarecovery clockrecoveryisaccomplishedwithaphase-locked-loop(pll).ifvalid dataisnotpresentonthereceiveinputs,thepllislockedtothe25mhz tx_clksignal.whenthesquelchcircuitdetectsvaliddataonthe receivetpinput,andifthedeviceisinthelinkpassstate,thepllinput isswitchedtotheincomingdataonthereceiveinputs.thepllthen locksontothetransitionsintheincomingsignaltorecovertheclock.the recovereddataclockisthenusedtogeneratethe25mhzrx_clk, whichclocksdataintothecontrollerinterfacesection. therecoveredclockextractedbytheplllatchesindatafromthetp receivertoperformdatarecovery.thedataisthenconvertedfroma singlebitstreamintonibble-widedatawordsaccordingtotheformat shownin figure2.3 2.3.9.210mbits/sclockanddatarecovery theclockrecoveryprocessfor10mbits/smodeisidenticaltothe100 mbits/smodeexcept therecoveredclockfrequencyisa2.5mhznibbleclock thepllisswitchedfromtx_clktothetpinputwhenthesquelch indicatesvaliddata theplltakesupto12transitions(bittimes)tolockontothe preamble,sosomeofthepreambledatasymbolsarelost.however, theclockrecoveryblockrecoversenoughpreamblesymbolstopass atleastsixnibblesofpreambletothereceivecontrollerinterfaceas shownin figure2.3 . thedatarecoveryprocessfor10mbits/smodeisidenticaltothatofthe 100mbits/smode.asmentionedinthemanchesterdecodersection,the datarecoveryprocessinherentlyperformsdecodingofmanchester encodeddatafromthetpinputs. 2-22functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3.10linkintegrityandautonegotiation thedevicecanbecon ? guredtoimplementeitherthestandardlink integrityalgorithmsortheautonegotiationalgorithm. thestandardlinkintegrityalgorithmsareusedsolelytoestablishalink toandfromaremotedevice.theautonegotiationalgorithmisusedto establishalinktoandfromaremotedevice and automaticallycon ? gure thedevicefor10or100mbits/sandhalf-orfull-duplexoperation.the differentstandardlinkintegrityalgorithmsfor10and100mbits/smodes aredescribedinfollowingsubsections. theautonegotiationalgorithminthedevicemeetsallrequirements speci ? edinieee802.3. 2.3.10.110base-tlinkintegrityalgorithm(10mbits/s) thedeviceimplementsthesame10base-tlinkintegrityalgorithmthat isde ? nedinieee802.3.thisalgorithmusesnormallinkpulses(nlps), whicharetransmittedduringidleperiods,todetermineifadevicehas successfullyestablishedalinkwitharemotedevice(calledlinkpass state).thetransmitlinkpulsemeetsthetemplaterequirementsde ? ned inieee802.3andshownin figure2.6 .refertoieee802.3formore detailsifneeded. blockdiagramdescription2-23 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure2.6linkpulseoutputvoltagetemplate(10mbits/s) 2.3.10.2100base-txlinkintegrityalgorithm(100mbits/s) becausetheieee802.3speci ? cationde ? nes100base-txtohavean activeidlesignal,thedeviceusesthesquelchcriteriaanddescrambler synchronizationalgorithmontheinputdatatodetermineifthedevice hassuccessfullyestablishedalinkwitharemotedevice(calledlink passstate).refertoieee802.3formoredetailsifneeded. 2.3.10.3autonegotiationalgorithm asstatedpreviously,theautonegotiationalgorithmisusedfortwo purposes: toestablishalinktoandfromaremotedevice toautomaticallycon ? gurethedeviceforeither10or100mbits/s operationandeitherhalf-orfull-duplexoperation. theautonegotiationalgorithmisthesamealgorithmde ? nedinieee 802.3clause28.autonegotiationusesaburstoflinkpulses,calledfast linkpulses(flps),topassupto16bitsofsignalingdatabackandforth betweenthedeviceandaremotedevice.thetransmitflppulsesmeet 0 bt 1.3 bt 2.0 bt + 50 mv 50 mv 42.0 bt 2.0 bt 0.85 bt 3.1 v 585 mv 3.1 v 0.5 v/ns + 50 mv 50 mv 0.5 bt 0.6 bt 300 mv 4.0 bt 4.0 bt 200 mv 0.25 bt 2-24functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. thetemplatespeci ? edinieee802.3andshownin figure2.6 .atiming diagramcontrastingnlpsandflpsisshownin figure2.7 . figure2.7nlpvsflplinkpulse toenableautonegotiationforachannel,asserttheautonegotiationpin (aneg),orsettheautonegotiationenable(aneg_en)bitinthemi serialportcontrolregister(register0).ifautonegotiationisenabled,any ofthefollowingeventsinitiatestheautonegotiationalgorithmforthe channel: powerup devicereset channelentersthelinkfailstate autonegotiationenable(aneg_en)bitinthemiserialportcontrol registerforthatportiscleared,thenset autonegotiationreset(aneg_rst)bitinthemiserialportcontrol registerisset onceanegotiationhasbeeninitiated,thedevice ? rstdeterminesifthe remotedevicehasautonegotiationcapability.iftheremotedeviceisnot autonegotiation-capableandisjusttransmittingeither10base-tor 100base-txsignals,thedevicesensesitandplacesitselfinthesame modeastheremotedevice.ifthedevicedetectsflpsfromtheremote device,theremotedeviceisdeterminedtohaveautonegotiation capability,andthedevicethenusesthevaluefromthephy autonegotiationadvertisementforthatporttoadvertiseitscapabilitiesto normal link pulse (nlp) tx_di tx_di fast link pulse (flp) clockclockclockclockclockclockclock datadatadatadatadatadata d0d1d2d3d14d15 blockdiagramdescription2-25 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. theremotedevice.thedevicenegotiationalgorithmmatchesits capabilitiestotheremotedevice scapabilitiesanddetermineswhat modethedeviceshouldbecon ? guredforaccordingtothepriority resolutionalgorithmde ? nedinieeee802.3clause28.afterthe negotiationprocessiscompleted,thedevicecon ? guresitselfforeither 10or100mbits/smodesandeitherhalf-orfull-duplexmodes (dependingontheoutcomeofthenegotiationprocess),andswitchesto eitherthe10base-tor100base-txlinkintegrityalgorithms(depending onwhichmodeautonegotiationenabled).refertoieee802.3clause 28formoredetails. 2.3.10.4autonegotiationoutcomeindication theoutcomeorresultoftheautonegotiationprocessisstoredinthe 10/100speeddetect(spd_det)andduplexdetect(dplx_det)bits inthemiserialportstatusoutput0register. 2.3.10.5autonegotiationstatus tomonitorthestatusoftheautonegotiationprocess,readthe autonegotiationacknowledgement(aneg_ack)bitinthemiserialport statusregister. 2.3.10.6autonegotiationenable/disable toenabletheautonegotiationalgorithm,settheautonegotiationenable bit(aneg_en)inthemiserialportcontrolregister,orasserttheaneg pin.todisabletheautonegotiationalgorithm,cleartheaneg_enbitor deasserttheanegpin. whentheautonegotiationalgorithmisenabled,thedevicehaltsall transmissionsincludinglinkpulsesfor1200to1500ms,entersthelink failstate,andrestartsthenegotiationprocess.whenthe autonegotiationalgorithmisdisabled,theselectionof100mbits/sor 10mbits/smodeisdeterminedwiththestateofthespeedbitinthemi serialportcontrolregisterandthehalf-orfull-duplexmodeis determinedwiththestateofthedplxbitinthemiserialportcontrol register. 2-26functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.3.10.7autonegotiationreset appropriatelysettingtheautonegotiationreset(aneg_rst)bitinthe miserialportcontrolregistercaninitiateorresettheautonegotiation algorithmatanytime. 2.3.11linkindication receivelinkdetectactivitycanbemonitoredtwoways: 1.thelinkdetectbit(link)inthemiserialportstatusregister indicateslinkactivitywhenitisset. 2.theledoutputpinscanbeprogrammedtoindicatelinkactivity. inthemiserialportcon ? gurationregister,settheledfunctionselect bits(led_def_[1:0])sothatlinkactivityisindicatedatthepled3nor pled0noutput.setthepled3_[1:0]andpled0_[1:0]bitsinthesame registerto0b11(normal).withthesesettings,ledsconnectedtothe pled3nandpled0npinswillre ? ectlinkactivity. wheneitherthepled3norpled0npinsareprogrammedtobealink detectoutput,theyaredrivenlowwheneverthedeviceisinthelink passstate.thepled3noutputisopen-drainwithapullupresistorand candriveanledfromv dd .thepled0noutputhasbothpullupand pulldowndrivertransistorsinadditiontoaweakpullupresistor,soitcan driveanledfromeitherv dd orgnd.boththepled3nandpled0n outputscanalsodriveanotherdigitalinput. see section2.3.13, leddrivers, page2-28 formoredetailsonhowto programtheledoutputpinstoindicatevariousconditions. 2.3.12collision collisionsoccurwhenevertransmitandreceiveoperationsoccur simultaneouslywhilethedeviceisinhalf-duplexmode. 2.3.12.1100mbits/s in100mbits/soperation,acollisionoccursandissensedwheneverthere issimultaneoustransmission(packettransmissionontpo+/-)and reception(non-idlesymbolsdetectedatthetp+/-input).whena blockdiagramdescription2-27 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. collisionisdetected,thecoloutputisasserted,tpdatacontinuesto betransmittedonthetwisted-pairoutputs,tpdatacontinuestobe receivedonthetwisted-pairinputs,andinternalcrsloopbackis disabled.afteracollisionisinprocess,crsisassertedandstays asserteduntilthereceiveandtransmitpacketsthatcausedthecollision areterminated. thecollisionfunctionisdisabledifthedeviceisinthefull-duplexmode, isinthelinkfailstate,orifthedeviceisinthediagnosticloopback mode. 2.3.12.210mbits/s acollisioninthe10mbits/smodeisidenticaltoonethe100mbits/s modeexcept the10mbits/ssquelchcriteriadeterminesreception therxd[3:0]outputsareforcedtoallzeros thecollisionsignal(col)isassertedwhenthesqetestis performed thecollisionsignal(col)isassertedwhenthejabberconditionhas beendetected. 2.3.12.3collisiontest totestthecontrollerinterfacecollisionsignal(col),setthecoltstbit inthemiserialportcontrolregister.whenthisbitisset,tx_enis loopedbackontocolandthetpoutputsaredisabled. 2.3.12.4collisionindication collisionsareindicatedthroughthecolpin,whichisassertedhigh everytimeacollisionoccurs.thedevicecanalsobeprogrammedto indicatecollisionsonthepled2noutput. inthemiserialportcon ? gurationregister,settheledfunctionselect bits(led_def_[1:0])sothatcollisionactivityisindicatedatthepled2n output.setthepled2_[1:0]bitsinthesameregisterto0b11(normal). withthesesettings,anledconnectedtothepled2npinwillre ? ect collisionactivity. 2-28functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. whenthepled2npinisprogrammedtobeacollisiondetectoutput,it isassertedlowfor100mseverytimeacollisionoccurs.thepled2n outputisopendrainwithapullupresistorandcandriveanledfrom v dd orcandriveanotherdigitalinput. see section2.3.13, leddrivers, page2-28 formoredetailsonhowto programtheledoutputpinstoindicatevariousconditions. 2.3.13leddrivers thepled[5:2]noutputsareopen-drainwithapullupresistorandcan driveledstiedtov dd .thepled[1:0]noutputshavebothpullupand pulldowndrivertransistorswithapullupresistor,sothepled[1:0]n outputscandriveledstiedtoeitherv dd orgnd. thepled[5:0]noutputscanbeprogrammedthroughthemiserialport con ? gurationregisterforthefollowingfunctions: normalfunction on off blink thepled[5:0]noutputsareprogrammedwiththeledoutputselectbits (pledn_[1:0])andthelednormalfunctionselectbits(led_def[1:0]) inthemiserialportcon ? gurationregister. 2.3.13.1ledoutputselectbits therearefoursetsofoutputselectbitsinmiserialportcon ? guration register,onesetforeachledoutputpin: pled3_[1:0]controlthepled3noutput pled2_[1:0]controlthepled2noutput pled1_[1:0]controlthepled1noutput pled0_[1:0]controlthepled0noutput thepledn_[1:0]bitsprogramtheoutputstooperateinthefollowing modes: blockdiagramdescription2-29 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. normaloperation(see section2.3.13.2, lednormalfunction selectbits ) blink steadyon(pled[3:0]npinlow) steadyoff(pled[3:0]npinhigh) table2.6 showstheencodingoftheoutputselectbits. 2.3.13.2lednormalfunctionselectbits whenthepled[5:0]npinsareprogrammedfortheirnormalfunctions (pledn_[1:0]=0b11),thepinoutputstatesindicatefourspeci ? ctypes ofevents.thelednormalfunctionselectbits(led_def[1:0])inthe miserialportcon ? gurationregisterdeterminethestatesofthepins,as indicatedin table2.7 and table2.8 . table2.6pledn_[1:0]outputselectbitencoding pledn_[1]pledn_[0]ledstateledpin 11normalledpinre ? ectsthefunctionsselectedwiththe led_def[1:0]bits 10ledblinkledoutputdrivercontinuouslytogglesatarateof100ms on,100msoff 01ledonledoutputdriverislow 00ledoffledoutputdriverishigh table2.7lednormalfunctionde ? nition led_def[1:0]pled5npled4npled3npled2npled1npled0n 0b11rcvactxmtactlinkcolfdx10/100 0b10rcvactxmtactlinkactfdx10/100 0b01rcvactxmtactlink+actcolfdx10/100 0b00 1 rcvactxmtactlink100actfdxlink10 1.theL80227powersupwiththeled_def[1:0]bitssettothedefaultvalueof0b00. 2-30functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. thedefaultnormalfunctionsforpled[5:0]narereceiveactivity, transmitactivity,link100,activity,fullduplex,andlink10,respectively. 2.4startofpacket thissectiondescribesstartofpacketoperationforboththe100mbits/s and10mbits/smodes. 2.4.1100mbits/s auniquestartofstreamdelimiter(ssd)indicatesthestartofpacketfor 100mbits/smode.thessdpatternconsistsoftwo/j/k/5bsymbols insertedatthebeginningofthepacketinplaceofthe ? rsttwopreamble symbols,asde ? nedinieee802.3clause24andshownin table2.4 and figure2.2 . the4b5bencodergeneratesthetransmitssdandinsertsthe/j/k/ symbolsatthebeginningofthetransmitdatapacketinplaceofthe ? rst two5bsymbolsofthepreamble,asshownin figure2.2 . table2.8ledeventde ? nition symbolde ? nition rcvactreceiveactivityoccurred;stretchpulseto100ms xmtacttransmitactivityoccurred;stretchpulseto100ms link100or10mbits/slinkdetected link+act100or10mbits/slinkdetectedoractivityoccurred;stretch pulseto100ms(linkdetectcausesledtobeon,activity causesledtoblink) actactivityoccurred;stretchpulseto100ms link100100mbit/slinkdetected colcollisionoccurred;stretchpulseto100ms fdxfull-duplexmodeenabled 10/10010mbits/smodeenabled(high),or100mbits/smode enabled(low) link1010mbits/slinkdetected endofpacket2-31 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. the4b5bdecoderdetectsthereceivepattern.todothis,thedecoder examinesgroupsof10consecutivecodebits(two5bwords)fromthe descrambler.betweenpackets,thereceiverdetectstheidlepattern (5b/i/symbols).whenintheidlestate,thedevicedeassertsthecrs andrx_dvpins. ifthereceiverisintheidlestateand10consecutivecodebitsfromthe receiverconsistofthe/j/k/symbols,thestartofpacketisdetected,data receptionbegins,and/5/5/symbolsaresubstitutedinplaceofthe/j/k/ symbols. ifthereceiverisintheidlestateand10consecutivecodebitsfromthe receiverareapatternthatisneither/i/i/nor/j/k/symbols,butcontain atleasttwononcontiguouszeros,activityisdetectedbutthestartof packetisconsideredtobefaultyandafalsecarrierindication(also referredtoasbadssd)issignaledtothecontrollerinterface. whenfalsecarrierisdetected,crsisasserted,rx_erisasserted, rx_dvremainsdeasserted,andtherxd[3:0]outputstateis0b1110 whilerx_erisasserted. ifthereceiverisintheidlestateand10consecutivecodebitsfromthe receiverconsistofapatternthatisneither/i/i/nor/j/k/symbolsbutdoes notcontainatleasttwononcontiguouszeros,thedataisignoredandthe receiverstaysintheidlestate. 2.4.210mbits/s becausetheidleperiodin10mbits/smodeisde ? nedtobewhenthere isnovaliddataonthetpinputs,thestartofpacketfor10mbits/smode isdetectedwhenthetpsquelchcircuitdetectsvaliddata.whenthe startofpacketisdetected,crsisassertedasdescribedin section 2.3.2, controllerinterface, page2-9 .see section2.3.8.4, squelch(10 mbits/s), page2-20 fordetailsonthesquelchalgorithm. 2.5endofpacket thissectiondescribesendofpacketoperationforboththe100mbits/s and10mbits/smodes. 2-32functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.5.1100mbits/s theendofstreamdelimiter(esd)indicatestheendofpacketfor100 mbits/smode.theesdpatternconsistsoftwo/t/r/4b5bsymbols insertedaftertheendofthepacket,asde ? nedinieee802.3clause24 andshownin table2.4 and figure2.2 . the4b5bencodergeneratesthetransmitesdandinsertsthe/t/r/ symbolsaftertheendofthetransmitdatapacket,asshownin figure2.2 . the4b5bdecoderdetectstheesdpatternwhentherearegroupsof10 consecutivecodebits(two5bwords)fromthedescramblerduringvalid packetreception. ifthe10consecutivecodebitsfromthereceiverduringvalidpacket receptionconsistofthe/t/r/symbols,theendofpacketisdetected, datareceptionisterminated,thecrsandrx_dvpinsareasserted,and /i/i/symbolsaresubstitutedinplaceofthe/t/r/symbols. ifthe10consecutivecodebitsfromthereceiverduringvalidpacket receptiondonotconsistof/t/r/symbols,butinsteadconsistof/i/i/ symbols,thepacketisconsideredtohavebeenterminatedprematurely andabnormally,andtheendofpacketconditionissignalledtothe controllerinterface. whentheprematureendofpacketconditionisdetected,therx_er signalisassertedforthenibbleassociatedwiththe ? rst/i/symbol detected,thenthecrsandrx_dvpinsaredeasserted. 2.5.210mbits/s theendofpacketfor10mbits/smodeisindicatedwiththestartofidle (soi)pulse.thesoipulseisapositivedoublewidepulsecontaininga manchestercodeviolationinsertedattheendofeverypacket. thetptransmittergeneratesthetransmitsoipulseandinsertsitatthe endofthedatapacketaftertx_enhasbeendeasserted.thetransmit waveshapershapesthetransmittedsoioutputpulseatthetpoutputto meetthepulsetemplaterequirementsspeci ? edinieee802.3clause14 andshownin figure2.8 . full-/half-duplexmode2-33 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure2.8soioutputvoltagetemplate(10mbits/s) thetpreceiversensesmissingdatatransitionsinordertodetectthe receivesoipulse.oncethesoipulseisdetected,datareceptionis endedandthecrsandrx_dvpinsaredeasserted. 2.6full-/half-duplexmode half-duplexmodeisthecsma/cdoperationde ? nedinieee802.3.it allowstransmissionorreception,butnotbothatthesametime.full- duplexoperationisamodethatallowssimultaneoustransmissionand reception.fullduplexinthe10mbits/smodeisidenticaltooperationin the100mbits/smode. thedevicecanbeforcedintoeitherthefull-orhalf-duplexmode,or thedevicecanuseautonegotiationtoautoselectfull-/half-duplex operation.whenachannelisplacedinfull-duplexmode: thecollisionfunctionisdisabled,and tx_entocrsloopbackisdisabled 0 bt 4.5 bt 6.0 bt + 50 mv 50 mv 45.0 bt 4.5 bt 2.5 bt 3.1 v 0.25 bt 2.25 bt 585 mv 3.1 v 0.5 v/ns 585 mv sin (2 (t/1 bt)) 0 t 0.25 bt and 225 t 2.5 bt 2-34functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.6.1forcingfull-/half-duplexoperation toindependentlyforceachannelintoeitherthefull-orhalf-duplex mode,settheduplexmodeselect(dplx)bitinthemiserialport controlregister,assumingthatautonegotiationisnotenabledwiththe aneg_enbitinthemiserialportcontrolregister. thedeviceautomaticallycon ? guresitselfforfull-orhalf-duplexmode. todothis,thedeviceusestheautonegotiationalgorithmtoadvertise anddetectfull-andhalf-duplexcapabilitiestoandfromaremote device.toenableautonegotiation,settheautonegotiationenable (aneg_en)bitinthemiserialportcontrolregister. toselecttheadvertisedfull/-half-duplexcapability,appropriatelysetthe bitsinthemiserialportautonegotiationadvertisementregister. autonegotiationfunctionalityisdescribedinmoredetailin section 2.3.10, linkintegrityandautonegotiation . 2.6.2full/halfduplexindication full-duplexdetectioncanbemonitoredthroughthedplx_detbitinthe miserialportstatusoutputregister,oritcanalsobeprogrammedto appearonthepled1npin. inthemiserialportcon ? gurationregister,settheledfunctionselect bits(led_def[1:0])sothatthefull-duplexconditionactivityisindicated atthepled1noutput.setthepled2_[1:0]bitsinthesameregisterto 0b11(normal).whenthepled1npinisprogrammedtobeafull-duplex detectoutput,itisassertedlowwhenthedeviceiscon ? guredfor full-duplexoperation.thepled1noutputhasbothpullupandpulldown drivertransistorsandaweakpullupresistor,soitcandriveanledfrom eitherv dd orgndandcanalsodriveadigitalinput. see section2.3.13, leddrivers, page2-28 formoredetailsonhowto programtheledoutputpinstoindicatevariousconditions. 2.6.3loopback 2.6.3.1internalcrsloopback tx_enisinternallyloopedbackontocrsduringeverytransmitpacket. thisinternalcrsloopbackisdisabledduringcollision,infull-duplex 10/100mbits/sselection2-35 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. mode,andinthelinkfailstate.in10mbits/smode,internalcrs loopbackisalsodisabledwhenjabberisdetected. 2.6.3.2diagnosticloopback settingtheloopbackbit(lpbk)inthemiserialportcontrolregister selectsthediagnosticloopbackmode.whendiagnosticloopbackis enabled,thetxd[3:0]dataisloopedbackontorxd[3:0],tx_enis loopedbackontocrs,rx_dvoperatesnormally,thetpreceiveand transmitpathsaredisabled,thetransmitlinkpulsesarehalted,andthe half-/full-duplexmodesdonotchange. 2.710/100mbits/sselection thedevicecanbeforcedintoeitherthe10or100mbits/smode,orit canuseautonegotiationtoautoselect10or100mbits/soperation. 2.7.1forcing10/100mbits/soperation toindependentlyforceeachchannelintoeitherthe10mbits/sor100 mbits/smode cleartheaneg_enbitinthemiserialportcontrolregister,and setthespeedselect(speed)bitinthemiserialportcontrol register 2.7.2autoselecting10/100mbits/soperation thedevicecanautomaticallycon ? gureitselffor10or100mbits/smode. todothis,itusestheautonegotiationalgorithmtoadvertiseanddetect 10and100mbits/scapabilitiestoandfromaremotedevice.settingthe autonegotiationenable(aneg_en)bitinthemiserialportcontrol registerenablesautonegotiation.appropriatelysettingthebitsinthemi serialportautonegotiationadvertisementregisterselectstheadvertised speedcapability.autonegotiationfunctionalityisdescribedinmoredetail in section2.3.10, linkintegrityandautonegotiation . 2-36functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 2.7.310/100mbits/sindication thechannel10/100mbits/sspeedcanbemonitoredthroughthe spd_detbitinthemiserialportchannelstatusoutputregister. inthemiserialportcon ? gurationregister,settheledfunctionselect bits(led_def[1:0])sothatthe10/100speedconditionisindicatedat thepled0noutput.setthepled_2[1:0]nbitsinthesameregisterto 0b11(normal).whenthepled0npinisprogrammedtobeaspeed detectoutput,itisassertedlowwhenthedeviceiscon ? guredfor100 mbits/soperation.thepled0noutputhasbothpullupandpulldown drivertransistorsandaweakpullupresistor,soitcandriveanledfrom eitherv dd orgndandcanalsodriveadigitalinput. see section2.3.13, leddrivers, page2-28 formoredetailsonhowto programtheledoutputpinstoindicatevariousconditions. 2.8jabber ajabberconditionoccursin10mbits/smodewhenthetransmitpacket exceedsapredeterminedlength.whenjabberisdetected,thetp transmitoutputsareforcedtotheidlestate,acollisionisasserted,and thejabregisterbitissetinthemiserialportstatusregister. clearingthejabberdisable(jab_dis)bitto0inthemiserialport con ? gurationregisterdisablesthejabberfunction. thejabberfunctionisdisabledinthe100mbits/smode. 2.9reset thedeviceisresetwhen 1.v dd isappliedtothedevice,or 2.theresetbit(rst)issetinthemiserialportcontrolregister,or 3.theresetnpinisasserted(low). whenresetoccursbecauseof(1)or(2),aninternalpower-onreset pulseisgeneratedthatresetsallinternalcircuits,forcesthemiserialport receivepolaritycorrection2-37 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. bitstotheirdefaultvalues,andlatchesinnewvaluesforthemiaddress. afterthepower-onresetpulsehas ? nished,theresetbit(rst)inthemi serialportcontrolregisterisclearedandthedeviceisreadyfornormal operation. whenresetisinitiatedbecauseof(3),thesameprocedureoccursexcept thedevicestaysintheresetstateaslongastheresetnpinisheld low.theresetnpinhasaninternalpulluptov dd .thedeviceis guaranteedtobereadyfornormaloperation50msafterthereset sequenceisinitiated. 2.10receivepolaritycorrection in10mbits/smode,thepolarityofthesignalonthetpreceiveinputis continuouslymonitored. astartofidle(soi)pulseissentattheendoftransmissioninorderto signaltoareceiverthattransmissionhasendedandtheidleperiodhas started.thesoipulseisapositivepulse.whenthesoipulseis detected,itindicatesthatreceivedataisnolongervalidandcausesthe devicetoturnonthereceivesquelchmechanism.linkpulsesare transmittedoccasionallyduringtheidleperiod. whenthedeviceispoweredup,itisassumedthatthepolarityiscorrect andnopolaritycorrectionoccurs.afterthat,receivepolarityis continuouslymonitoredbycheckingthepolarityofthesoipulses(they arealwaysexpectedtobepositivepulses).ifthreeconsecutivesoi pulsesindicateincorrectpolarityonthetpreceiveinput,thepolarityis internallydeterminedtobeincorrect.inthiscase,thereversepolarity detectbit(rpol)issetinthemiserialportstatusoutputregister. thedeviceautomaticallycorrectsforthereversepolaritycondition, providedtheautopolarityfeatureisnotdisabled.todisableautopolarity, settheautopolaritydisablebit(apol_dis)inthemiserialport con ? gurationregister. nopolaritydetectionorcorrectionisneededinthe100mbits/smode. 2-38functionaldescription copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. L8022710base-t/100base-txethernetphytechnicalmanual3-1 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. chapter3 signaldescriptions thischapterdescribesthedevicesignals.itcontainsthefollowing sections: section3.1, mediainterfacesignals section3.2, controllerinterfacesignals(mii) section3.3, managementinterface(mi)/ledsignals section3.4, ledsignals section3.5, miscellaneoussignals section3.6, powersupply figure3.1 isalogicdiagramforthedevice. 3-2signaldescriptions copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure3.1devicelogicdiagram 3.1mediainterfacesignals rext transmitcurrentseti aresistorconnectedbetweentherextpinandgnd setstheoutputcurrentforthetptransmitoutputs. tpo+twisted-pairtransmitoutput(positive)o thetpo+pinfunctionsasthepositivesignalinthe twisted-pairoutput. tpo-twisted-pairtransmitoutput(negative)o thetpo-pinfunctionsasthenegativesignalinthe twisted-pairoutput. rext media interface oscin tx_en controller interface management interface mdc mdio mda4n pled4n pled3n/mda3n pled2n/mda2n pled1n/mda1n leds/ col resetn miscellaneous 10/100 mbit/s ethernet physical layer device (phy) (mii) tpi tpi tpo tpo tx_er txd[3:0] rxd[3:0] rx_en rx_clk tx_clk rx_dv pled5n pled0n/mda0n rx_er mi address crs nc speed dplx aneg controllerinterfacesignals(mii)3-3 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. tpi+twisted-pairreceiveinput(positive)i thetpi+pinfunctionsasthepositivesignalinthe twisted-pairinput. tpi-twisted-pairreceiveinput(negative)i thetpi-pinfunctionsasthenegativesignalinthe twisted-pairinput. 3.2controllerinterfacesignals(mii) crscarriersenseoutputo thecrsoutputisassertedhighwhenvaliddatais detectedonthereceivetpinputs.crsisclockedouton thefallingedgeofrx_clk. oscinclockoscillatorinputi theremustbeeithera25mhzcrystalbetweenthispin andgndora25mhzclockappliedtothispin.tx_clk outputisgeneratedfromthisinput. rx_clkreceiveclockoutputo receivedataonrxd,rx_dv,andrx_erisclockedout toanexternalcontrolleronthefallingedgeofrx_clk. rxd[3:0]receivedataoutputo rxd[3:0]containreceivenibbledatafromthetpinput, andtheyareclockedoutonthefallingedgeofrx_clk. rx_dvreceivedatavalidoutputo rx_dvisassertedhighwhenvaliddecodeddatais presentontherxdoutputs.rx_dvisclockedoutonthe fallingedgeofrx_clk. rx_enreceiveenableinputi whenrx_enishigh,allofthereceiveoutputs (rx_clk,rxd[3:0],rx_dv,rx_er,col)areenabled. whenrx_enislow,theoutputsareinahigh-imped- ancestate. rx_erreceiveerroroutputo rx_erisassertedhighwhenacodingerrororother speci ? ederrorsaredetectedonthereceivetwisted-pair inputs.thesignalisclockedoutonthefallingedgeof rx_clk. 3-4signaldescriptions copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. tx_clktransmitclockoutputo transmitdatafromthecontrollerontxd,tx_en,and tx_erisclockedinontherisingedgeoftx_clkand oscin. txd[3:0]transmitdatainputi txd[3:0]containinputnibbledatatobetransmittedon thetpoutputs,andtheyareclockedinontherising edgeoftx_clkandoscinwhentx_enisasserted. tx_entransmitenableinputi tx_enmustbeassertedhightoindicatethatdataon txdandtx_erisvalid.tx_erisclockedinontheris- ingedgeoftx_clkandoscin. tx_ertransmiterrorinputi thetxerpin,whenasserted,causesaspecialpattern tobetransmittedonthetwisted-pairoutputsinplaceof normaldata,anditisclockedinontherisingedgeof tx_clkwhentx_enisasserted. 3.3managementinterface(mi)/ledsignals mdcmiclocki themdcclockshiftsserialdatafortheinternalregisters intoandoutofthemdiopinonitsrisingedge. mda4n address4inputpullupo.d.i duringpoweruporreset,thispinishigh-impedanceand thelevelonthispinislatchedinasthephysicaldevice addressmda4forthemiserialport mdiomidatai/o thisbidirectionalpincontainsserialdatafortheinternal registers.thedataonthispinisclockedinandoutofthe deviceontherisingedgeofmdc. pled3n/mda3npullupo.d.i/o programmableledoutput/miaddressbit thedefaultfunctionofthispinistobea100mbits/slink detectoutput.thispincanalsobeprogrammedthrough themiserialporttoindicateothereventsorbeusercon- trolled.thispincandriveanledfromv dd . managementinterface(mi)/ledsignals3-5 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. whenprogrammedasa100mbits/slinkdetectoutput (default): duringpoweruporreset,thispinishigh-impedanceand thelevelonthispinislatchedinasthephysicaldevice addressmda3nforthemiserialport. pled2n/mda2npullupo.d.i/o programmableledoutput/miaddressbit thedefaultfunctionofthispinistobeanactivitydetect output.thispincanalsobeprogrammedthroughthemi serialporttoindicateothereventsorbeusercontrolled. thispincandriveanledfromv dd . whenprogrammedasanactivitydetectoutput(default): duringpoweruporreset,thispinishigh-impedanceand thelevelonthispinislatchedinasthephysicaldevice addressmda2nforthemiserialport. pled1n/mda1npullupo.d.i/o programmableledoutput/miaddressbit thedefaultfunctionofthispinistobeafullduplex detectoutput.thispincanalsobeprogrammedthrough themiserialporttoindicateothereventsorbeuser controlled.thispincandriveanledfrombothv dd and gnd. whenprogrammedasfullduplexdetectoutput (default): pinfunction highnolinkdetect low100mbits/slinkdetected pinfunction highnoactivity lowtransmitorreceivepacketoccurred(heldlowfor100 ms) pinfunction highhalf-duplex lowfull-duplex 3-6signaldescriptions copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. duringpoweruporreset,thispinishigh-impedanceand thelevelonthispinislatchedinasthephysicaladdress deviceaddressmda1nforthemiserialport. pled0n/mda0npullupo.d.i/o programmableledoutput/miaddressbit thedefaultfunctionofthispinistobea10mbits/slink detectoutput.thispincanalsobeprogrammedthrough themiserialporttoindicateothereventsorbeuser controlled. thispincandriveanledfrombothv dd andgnd. whenprogrammedas10mbits/slinkdetectoutput (default): duringpoweruporreset,thispinishigh-impedanceand thevalueonthispinislatchedinastheaddressmda0n forthemiserialport. 3.4ledsignals pled5nreceiveledoutputpullupo.d.o thefunctionofthispinistobeareceiveactivitydetect output.thispincanalsodriveanledfromv dd . high=noreceiveactivity low=receivepacketoccurred:holdlowfor100ms pled4ntransmitledoutputpullupo.d.o thefunctionofthispinistobeatransmitactivitydetect output.thispincanalsodriveanledfromv dd . high=notransmitactivity low=transmitpacketoccurred:holdlowfor100ms pinfunction highnodetect low10mbits/slinkdetected miscellaneoussignals3-7 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 3.5miscellaneoussignals anegautonegotiationinputi thispincontrolautonegotiationoperation. colcollisionoutputo colisassertedhighwhenacollisionbetweentransmit andreceivedataisdetected. dplxfull/halfduplexselectinputi whentheanegpinislow,thedplxpinselects half/fullduplexoperation. whentheanegpinishigh,thedplxpinisignored andthehalf/fullduplexoperationiscontrolledfromthe duplexmodeselectbit(dplx)inthemiserialportcon- trolregisterortheautonegotiationoutcome. ncnoconnect thesepinsarereservedforfutureuseandshouldbeleft ? oatingforproperoperation. resetnhardwareresetinputpullupi pinmeaning highautonegotiationison. autonegotiationenableiscontrolledfromthe aneg_enbit,10/100mbits/soperationiscontrolled fromthespeedbit,andhalf/fullduplexoperationis controlledfromthedplxbit. lowautonegotiationisoff. 10/100mbits/soperationiscontrolledfromthespeed pinandhalf/fullduplexoperationiscontrolledfromthe dplxpin. pinmeaning highfullduplexoperation lowhalfduplexoperation pinmeaning highnormal lowdeviceinresetstate.resetis ? nished100msafter resetngoeshigh. 3-8signaldescriptions copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. speedspeedselectinputi whentheanegpinislow,thespeedpinselects 10/100mbits/soperation. whentheanegpinishigh,thispinisignoredandthe speedisdeterminedfromthespeedselectbit(speed) inthemiserialportcontrolregisterorthe autonegotiationoutcome. 3.6powersupply gndgroundi thegroundpinsmustbeconnectedtoground(0volts). vddpositivesupplyi thev dd pinsmustbeconnectedto3.3 5%volts. pinmeaning high100mbits/soperation low10mbits/soperation L8022710base-t/100base-txethernetphytechnicalmanual4-1 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. chapter4 registers thischaptercontainsadescriptionoftheregistersaccessedoverthe managementinterface(mi)serialinterface.itcontainsthefollowing sections: section4.1, bittypes section4.2, miserialportregistersummary section4.3, registers forfurtherinformationabouttheoperationofthemiserialinterface,see chapter5, managementinterface. 4.1bittypes becausetheserialportisbidirectional(capableofbothreadandwrite operations),therearemanytypesofbits.thefollowingbittype de ? nitionsaresummarizedin table4.1 : writebits(w)areinputsduringawritecycleandarehigh impedanceduringareadcycle readbits(r)areoutputsduringareadcycleandhighimpedance duringawritecycle read/writebits(r/w)areactuallywritebitsthatcanbereadout duringareadcycle r/wscbitsarer/wbitsthatareself-clearingafterasetperiodof timeorafteraspeci ? ceventhascompleted r/llbitsarereadbitsthatlatchthemselveswhentheygolow,and theystaylowuntilread.aftertheyareread,theyareresethigh. r/lhbitsarethesameasr/llbits,exceptthattheylatchhigh. 4-2registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. r/ltarereadbitsthatlatchthemselveswhenevertheymakea transitionorchangevalue,andtheystaylatcheduntiltheyareread. afterr/ltbitsareread,theyareupdatedtotheircurrentvalue. table4.1miregisterbittypede ? nition symbolname de ? nition writecyclereadcycle wwriteinputnooperation,hi-z rreadnooperation,hi-zoutput r/wread/writeinputoutput r/wscread/write, self-clearing inputoutput (clearsitselfaftertheoperationcompletes) r/llread/latching low nooperation,hi-zoutput whenthebitgoeslow,itislatched. whenthebitisread,itisupdated. r/lhread/latching high nooperation,hi-zoutput whenthebitgoeshigh,itislatched. whenthebitisread,itisupdated. r/ltread/latchingon transition nooperation,hi-zoutput whenthebittransitions,thebitislatched. whenthebitisread,thebitisupdated. miserialportregistersummary4-3 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.2miserialportregistersummary thefollowingtablessummarizethedeviceregistersaccessiblethrough themiserialport. controlregister(register0) statusregister(register1) phyid#1register(register2) C phyid#2register(register3) 15141312111098 rstlpbkspeedaneg_enpdnmii_disaneg_rstdplx 76 0 coltstreserved 1514131211108 cap_t4cap_txfcap_txhcap_tfcap_threserved 76543210 reservedcap_supraneg_ackrem_fltcap_aneglinkjabexreg 15141312111098 oui3oui4oui5oui6oui7oui8oui9oui10 76543210 oui11oui12oui13oui14oui15oui16oui17oui18 15141312111098 oui19oui20oui21oui22oui23oui24part5part4 76543210 part3part2part1part0rev3rev2rev1rev0 4-4registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. autonegotiationadvertisementregister(register4) autonegotiationremoteendcapabilityregister(register5) con ? gurationregister(register17) statusoutputregister(register18) 151413121098 npackrfreservedt4tx_fdx 765410 tx_hdx10_fdx10_hdxreservedcsma 151413121098 npackrfreservedt4tx_fdx 765410 tx_hdx10_fdx10_hdxreservedcsma 15141312111098 pled3_1pled3_0pled2_1pled2_0pled1_1pled1_0pled0_1pled0_0 743210 led_def1led_def0apol_disjab_dismregreserved 15 8 reserved 754320 reservedspd_detdplx_detreserved registers4-5 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.3registers thissectioncontainsadescriptionofeachofthebitsineachregister. 4.3.1controlregister(register0) thedefaultvalueforthisregisteris0x3400. rstresetr/wsc15 lpbkloopbackenabler/w14 speedspeedselectr/w13 aneg_enautonegotiationenabler/w12 15141312111098 rstlpbkspeedaneg_enpdnmii_disaneg_rstdplx 76 0 coltstreserved bitmeaning 1reset.thebitisbitself-clearinginlessthanorequalto 200 safterreset ? nishes. 0normal(default) bitmeaning 1loopbackmodeenabled 0normal(default) bit 1 meaning 1100mbit/s(100base-tx)(default) 010mbit/s(10base-t) 1.thespeedbitiseffectiveonlywhenautonegotiationisoff bitmeaning 11=autonegotiationenabled(default) 00=disabled 4-6registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. pdnpowerdownenabler/w11 mii_dismiiinterfacedisabler/w10 aneg_rstautonegotiationresetr/wsc9 dplxduplexmodeselectr/w8 coltstcollisiontestenabler/w7 rreservedr[6:0] thesebitsarereservedandmustremainatthedefault valueof0x00forproperdeviceoperation. bitmeaning 1powerdown 0normal(default) bit 1 meaning 0miiinterfacedisable 1normal(default) 1.ifmda[4:0]nisnotreadas0b11111,themii_disdefault valueischangedto0. bitmeaning 1restartautonegotiationprocess.thebitisself-clearing afterresetis ? nished 0normal(default) bit 1 meaning 1full-duplex(default) 0half-duplex 1.thisbitiseffectiveonlywhenautonegotiationisoff bitmeaning 1collisiontestenabled 0normal(default) registers4-7 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.3.2statusregister(register1) thedefaultvalueofthisregisteris0x7809. cap_t4100base-t4capabler15 cap_txf100base-txfullduplexcapabler14 cap_txh100base-txhalfduplexcapabler13 cap_tf10base-tfullduplexcapabler12 cap_th10base-thalfduplexcapabler11 1514131211108 cap_t4cap_txfcap_txhcap_tfcap_threserved 76543210 reservedcap_supraneg_ackrem_fltcap_aneglinkjabexreg bitmeaning 1capableof100base-t4operation 0notcapableof100base-t4operation(default) bitmeaning 1capableof100base-txfull-duplex(default) 0notcapableof100base-txfull-duplex bitmeaning 1capableof100base-txhalf-duplex(default) 0notcapableof100base-txhalf-duplex bitmeaning 1capableof10base-tfull-duplex(default) 0notcapableof10base-tfull-duplex bitmeaning 1capableof10base-thalfduplex(default) 0notcapableof10base-thalfduplex 4-8registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. rreservedr[10:7] thesebitsarereservedandmustremainatthedefault valueof0x0forproperdeviceoperation cap_suprmipreamblesuppressioncapabler6 aneg_ackautonegotiationacknowledgmentr5 rem_fltremotefaultdetectr/lh4 cap_anegautonegotiationcapabler3 linklinkstatusr/ll2 bitmeaning 1capableofacceptingmiframeswithpreamble suppression 0notcapableofacceptingmiframeswithpreamble suppression(default) bitmeaning 1autonegotiationacknowledgmentprocesscomplete 0autonegotiationnotcomplete(default) bitmeaning 1remotefaultdetect.therem_fltbitissetwhenremote fault(rf)bitissetintheautonegotiationremoteend capabilityregister. 0noremotefault(default) bitmeaning 1capableofautonegotiation(default) 0notcapableofautonegotiation bitmeaning 1linkdetected. 0linknotdetected(default) registers4-9 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. jabjabberdetectr/lh1 exregextendedregistercapabler0 4.3.3phyid1register(register2) oui[3:18]companyid,bits3 C 18r[15:0] oui[3:18]inthisregisterandoui[19:24]ofthephyid2 registermakeupthelsioui,whosedefaultvalueis 0x00.a07d.thetablebelowshowsthedefaultbitposi- tionsfortheentireoui ? eld: bitmeaning 1jabberdetected 0normal(default) bitmeaning 1extendedregistersexist(default) 0extendedregistersdonotexist 15141312111098 oui3oui4oui5oui6oui7oui8oui9oui10 76543210 oui11oui12oui13oui14oui15oui16oui17oui18 bitdefaultvaluehexvalue oiu2400x7 oiu231 oiu221 oiu211 oiu2010xd oiu191 oiu180 oiu171 oiu1610xa oiu150 oiu141 oiu130 oiu1200x0 oiu110 oiu100 oiu90 4-10registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.3.4phyid2register(register3) oui[19:24]companyid,bits19 C 24r[15:10] oui[19:24]inthisregisterandoui[3:18]ofthephyid1 registermakeupthelsioui,whosedefaultvalueis 0x00.a07d.seethetableinthephyid1descriptionfor adescriptionoftheentireoui ? eld. part[5:0]manufacturer spartnumberr[9:4] thedefaultvalueforthis ? eldis0x04.thetablebelow showsthedefaultbitpositionsforthepart[5:0] ? eld: rev[3:0]manufacturer srevisionnumberr[3:0] thedefaultvalueforthis ? eldis0x0. oiu800x0 oiu70 oiu60 oiu50 oiu400x0 oui30 15141312111098 oui19oui20oui21oui22oui23oui24part5part4 76543210 part3part2part1part0rev3rev2rev1rev0 bitdefaultvaluehexvalue bitdefaultvaluehexvalue part[5]0 0x0 part[4]0 part[3]0 0x4 part[2]1 part[1]0 part[0]0 registers4-11 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.3.5autonegotiationadvertisementregister(register4) thedefaultvalueforthisregisteris0x01e1. npnextpageenabler15 ackacknowledger14 rfremotefaultr/w13 rreservedr/w[12:10] thesebitsarereservedandmustremainatthedefault valueof0b00forproperdeviceoperation t4100base-t4capabler/w9 151413121098 npackrfreservedt4tx_fdx 765410 tx_hdx10_fdx10_hdxreservedcsma bitmeaning 1nextpage 0nonextpage(default) bitmeaning 1autonegotiationwordrecognized 0notrecognized(default) bitmeaning 1autonegotiationremotefaultdetect 0noremotefaultdetect(default) bitmeaning 1capableof100base-t4operation 0notcapable(default) 4-12registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. tx_fdx100base-txfullduplexcapabler/w8 tx_hdx100base-txhalfduplexcapabler/w7 10_fdx10base-txfullduplexcapabler/w6 10_hdx10base-txhalfduplexcapabler/w5 rreservedr/w[4:1] thesebitsarereservedandmustremainatthedefault valueof0x0forproperdeviceoperation csmacsma802.3capabler/w0 bitmeaning 1capableof100base-txfullduplexoperation(default) 0notcapable bitmeaning 1capableof100base-txhalfduplexoperation(default) 0notcapable bitmeaning 1capableof10base-tfull-duplexoperation(default) 0notcapable bitmeaning 1capableof10base-thalf-duplexoperation(default) 0notcapable bitmeaning 1capableof802.3csma 1 operation(default) 0notcapable 1.carrier-sense,multiple-access registers4-13 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.3.6autonegotiationremoteendcapabilityregister(register5) thedefaultvalueforthisregisteris0x0000. npnextpageenabler15 5 ackacknowledger14 rfremotefaultr13 rreservedr[12:10] thesebitsarereservedandmustremainatthedefault valueof0b00forproperdeviceoperation t4100base-t4capabler9 151413121098 npackrfreservedt4tx_fdx 765410 tx_hdx10_fdx10_hdxreservedcsma bitmeaning 1nextpageexists 0nonextpage(default) bitmeaning 1receivedautonegotiationwordrecognized 0notrecognized(default) bitmeaning 1autonegotiationremotefaultdetect 0noremotefault(default) bitmeaning 1capableof100base-t4operation 0notcapable(default) 4-14registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. tx_fdx100base-txfullduplexcapabler8 tx_hdx100base-txhalfduplexcapabler7 10_fdx10base-txfullduplexcapabler6 10_hdx10base-txhalfduplexcapabler5 rreservedr[4:1] thesebitsarereservedandmustremainatthedefault valueof0x0forproperdeviceoperation csmacsma802.3capabler0 bitmeaning 1capableof100base-txfullduplexoperation 0notcapable(default) bitmeaning 1capableof100base-txhalfduplexoperation 0notcapable(default) bitmeaning 1capableof10base-tfullduplexoperation 0notcapable(default) bitmeaning 1capableof10base-thalfduplexoperation 0notcapable(default) bitmeaning 1capableof802.3csma 1 operation 0notcapable(default) 1.carrier-sense,multiple-access registers4-15 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 4.3.7con ? gurationregister(register17) thedefaultvalueforthisregisteris0xff00. pled3_[1:0]nprogrammableled3outputselectr/w[15:14] pled2_[1:0]nprogrammableled2outputselectr/w[13:12] 15141312111098 pled3_1npled3_0npled2_1npled2_0npled1_1npled1_0npled0_1npled0_0n 743210 led_def1led_def0apol_disjab_dismregreserved pled3_1npled3_0nmeaning 11normal:pled3npinstateis determinedfromtheled_def[1:0]bits (defaultislink100). 0b11isthedefaultforthesebits 10ledtiedtopled3nblinks(toggles100 mslow,then100mshigh) 01ledtiedtopled3nonsteady (pled3noutputlow) 00ledtiedtopled3noffsteady (pled3noutputhigh) pled2_1npled2_0nmeaning 11normal:pled2npinstateis determinedfromtheled_def[1:0] bits(defaultisactivity). 0b11isthedefaultforthesebits 10ledtiedtopled2nblinks(toggles 100mslow,then100mshigh) 01ledtiedtopled2nonsteady (pled2noutputlow) 00ledtiedtopled2noffsteady (pled2noutputhigh) 4-16registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. pled1_[1:0]nprogrammableled1outputselectr/w[11:10] pled0_[1:0]nprogrammableled0outputselectr/w[9:8] led_def_[1:0] lednormalfunctionselectr/w[7:6] see table2.7 on page2-29 forthesebitde ? nitions. apol_disautopolaritydisabler5 pled1_1npled1_0nmeaning 11normal:pled1npinstateisdetermined fromtheled_def[1:0]bits(defaultis full-duplex). 0b11isthedefaultforthesebits 10ledtiedtopled1nblinks(toggles 100mslow,then100mshigh) 01ledtiedtopled1nonsteady (pled1noutputlow) 00ledtiedtopled1noffsteady (pled1noutputhigh) pled3_1npled3_0nmeaning 11normal:pled0npinstateis determinedfromtheled_def[1:0]bits (defaultislink10). 0b11isthedefaultforthesebits 10ledtiedtopled0nblinks(toggles 100mslow,then100mshigh) 01ledtiedtopled0nonsteady (pled0noutputlow) 00ledtiedtopled0noffsteady (pled0noutputhigh) bitmeaning 1autopolaritycorrectiondisabled 0normal(default) registers4-17 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. jab_disjabberdisabler4 mregmultipleregisteraccessenabler3 rreservedr[2:0] thesebitsarereservedandmustremainatthedefault valueof0x0forproperdeviceoperation. 4.3.8channelstatusoutput0register(register18) thedefaultvalueforthisregisteris0x0000. spd_det100/10mbits/sspeeddetectr7 dplx_detduplexdetectr6 rreservedr[5:0] thesebitsarereservedandmustremainatthedefault valueof0x0forproperdeviceoperation. bitmeaning 1jabberdisabled 0jabberenabled(default) bitmeaning 1multipleregisteraccessenabled 0nomultipleregisteraccess(default) 15 8 reserved 7650 spd_detdplx_detreserved bitmeaning 1deviceisin100mbits/smode(100base-tx) 0deviceisin10mbits/smode(10base-t) bitmeaning 1deviceisoperatinginfull-duplex 0deviceisoperatinginhalf-duplex 4-18registers copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. L8022710base-t/100base-txethernetphytechnicalmanual5-1 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. chapter5 managementinterface thischapterdescribesthemanagementinterface,overwhichthe internaldeviceregistersareaccessed.itcontainsthefollowingsections: section5.1, signaldescription section5.2, generaloperation section5.3, framestructure section5.4, registerstructure themanagementinterface,referredtoasthemiserialport,isa7-pin bidirectionallinkthroughwhichtheinternaldeviceregistersare accessed.theinternalregisterbitscontrolthecon ? gurationand capabilitiesofthedevice,andre ? ectdevicestatus. themiserialportprovidesaccesstoeightinternalregistersandmeets allieee802.3speci ? cationsforthemanagementinterface. 5.1signaldescription themiserialporthassixpins: mdc C serialshiftclockinputpin mdio C bidirectionaldatapin mda[3:0]n C physicaladdresspins themda[3:0]npinscon ? gurethedeviceforaparticularaddress,from 0b0000to0b1111,suchthat16devicescanexistinthesameaddress domainandeachcanbeaddressedseparatelyoverthemiserialport. whenanmireadorwritecycleoccurs,thedevicecomparesthe internallyinvertedandlatchedstateofthemda[4:0]npinstothe 5-2managementinterface copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. phyad[4:0]addressbitsofthemiframe.ifthestatescompare,the deviceknowsitisbeingaddressed. themda[3:0]ninputssharethesamepinsasthepled[3:0]nled outputs,respectively.atpoweruporreset,theledoutputdriversare 3-statedforanintervalcalledthepower-onresettime.duringthe power-onresettime,thelevelofthesepinsislatchedintothedevice, inverted,andusedasthemiserialportphysicaldeviceaddress. 5.2generaloperation themiserialportisidlewhenatleast32continuous1saredetectedon thebidirectionalmdiodatapinandremainsidleaslongascontinuous 1saredetected.duringidle,themdiooutputdriverisinthehigh- impedancestate.whenthemiserialportisintheidlestate,a0b01 patternonthemdiopininitiatesaserialshiftcycle.controlandaddress bitsareclockedintomdioonthenext14risingedgesofmdc(the mdiooutputdriverisstillinahigh-impedancestate).ifmultipleregister accessisnotenabled,dataiseithershiftedinoroutonmdioonthe next16risingedgesofmdc,dependingonwhetherawriteorreadcycle wasselectedwiththereadandwriteoperationbits.afterthe32 mdccycleshavebeencompleted onecompleteregisterhasbeenreadorwritten theserialshiftprocessishalted dataislatchedintothedevice themdiooutputdrivergoesintoahigh-impedancestate. anotherserialshiftcyclecannotbeinitiateduntiltheidleconditionis detectedagain(atleast32continuous1s). figure5.1 showsatiming diagramforamiserialportcycle. generaloperation5-3 rev.bcopyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. f i g u r e 5 . 1 m i s e r i a l p o r t f r a m e t i m i n g d i a g r a m w r i t e c y c l e m d c m d i o s t o p p h y a d r e g a d t a d a t a w r i t e b i t s p h y c l o c k s i n d a t a o n r i s i n g e d g e s o f m d c w i t h t s = 1 0 n s m i n i m u m a n d t h = 1 0 n s m i n i m u m r e a d c y c l e m d c m d i o s t o p p h y a d r e g a d t a d a t a w r i t e b i t s p h y c l o c k s i n d a t a o n r i s i n g e d g e s o f m d c w i t h r e a d b i t s p h y c l o c k s o u t d a t a o n r i s i n g e d g e s o f m d c w i t h t s = 1 0 n s m i n i m u m , a n d t h = 1 0 n s m i n i m u m t d = 2 0 n s m a x i m u m n o t e : s t = s t a r t b i t s , o p = o p e r a t i o n b i t s ( r e a d o r w r i t e ) , p h a d = p h y a d d r e s s , r e g a d = r e g i s t e r a d d r e s s , t a = t u r n a r o u n d b i t s f o r m o r e d e t a i l e d i n f o r m a t i o n o n t h e t i m i n g r e l a t e d t o t s , t h , a n d t d , p l e a s e s e e c h a p t e r 6 , s p e c i ? c a t i o n s . 5-4managementinterface copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 5.3framestructure thestructureoftheserialportframeisshownin figure5.2 andatiming diagramisshownin figure5.1 .eachserialportaccesscycleconsists of32bits(or144bitsifmultipleregisteraccessisenabledand regad[4:0]=0b11111),exclusiveofidle.the ? rst16bitsoftheserial portcyclearealwayswritebitsandareusedforcontrolandaddressing. thelast16bitsaredatathatiswrittentoorreadfromadataregister. the ? rsttwobitsin figure5.2 and figure5.1 arestartbits(st[1:0])and mustbewrittenasa0b01fortheserialportcycletocontinue.thenext twobitsarethereadandwritebits,whichdeterminewhetherthe registersarebeingreadorwritten.thenext ? vebitsarethephydevice addressbits(phyad[4:0]),andtheymustmatchtheinvertedvalues latchedfromthemda[4:0]npinsduringthepoweronresettimefor accesstocontinue. thenext ? vebitsareregisteraddressselect(regad[4:0])bits,which selectoneoftheeightregistersforaccess.thenexttwobitsare turnaround(ta)bits,whicharenotactualregisterbitsbutprovidethe deviceextratimetoswitchthemdiopinfunctionfromawritepintoa readpin,ifnecessary.the ? nal16bitsofthemiserialportcycleare writtentoorreadfromthespeci ? cdataregisterthattheregisteraddress bits(regad[4:0])designate. figure5.2 showsthemiframestructure. idleidlepatternw thesebitsareanidlepattern.thedevicedoesnot initiateanmicycleuntilitdetectsanidlepatternofat least32consecutive1s. st[1:0]startbitsw whenst[1:0]=01,amiserialportaccesscyclestarts. readreadselectw whenthereadbitis1,itdesignatesareadcycle. figure5.2miserialframestructure idlest[1:0]readwritephyad[4:0]regad[4:0]ta[1:0]d[15:0] registerstructure5-5 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. writewriteselectw whenthewritebitis1,itdesignatesawritecycle. phyad[4:0]physicaldeviceaddressw whenthephyad[4:0]bitsmatchtheinvertedlatched valueofthemda[4:0]npins,thedevice smiserialportis selectedforoperation. regad[4:0]registeraddressw theregad[4:0]bitsdeterminethespeci ? cregisterto access. ta[1:0]turnaroundtimer/w thesebitsprovidesometurnaroundtimeformdioto allowittoswitchtoawriteinputorreadoutput,as needed.whenread=1,ta[1:0]=z0;when write=1,ta[1:0]=0b10 . d[15:0]datarorw these16bitscontaindatatoorfromoneoftheregisters selectedwiththeregisteraddressbitsregad[4:0]. 5.4registerstructure thedevicehaseight16-bitregisters.amapoftheregistersisshownin section4.2, miserialportregistersummary .see chapter4, registers foracompletedescriptionofeachregister. theeightregistersconsistofsixregistersthatarede ? nedbyieee802.3 speci ? cations(registers0to5)andtworegistersthatareuniquetothe device(registers17and18). table5.1 givesasummaryofthefunctions ofeachregister 5-6managementinterface copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. . table5.1miserialportregistersummary registernamedescription 0controlregisterstoresvariouscon ? gurationbits 1statusregistercontainsdevicecapabilityandstatusoutputbits 2phyid1containanidenti ? cationcodeuniquetothedevice 3phyid2 4autonegotiation advertisement containsbitsthatcontroltheoperationoftheautonegotiation algorithm 5autonegotiation remoteend capability containsbitsthatre ? ecttheautonegotiationcapabilitiesofthelink partner sphy 17con ? gurationstoresvariouscon ? gurationbits 18channelstatus output0 containsstatus L8022710base-t/100base-txethernetphytechnicalmanual6-1 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. chapter6 speci ? cations thischaptercontainsthecompleteelectrical,timing,andmechanical speci ? cationsforthedevice.itcontainsthefollowingsections: section6.1, absolutemaximumratings section6.2, electricalcharacteristics section6.3, acelectricalcharacteristics section6.4, pinoutsandpackagedrawings section6.5, mechanicaldrawing 6.1absolutemaximumratings table6.1 showsthedeviceabsolutemaximumratings.thesearelimits which,ifexceeded,couldcausepermanentdamagetothedeviceor affectdevicereliability.allvoltagesarespeci ? edwithrespecttognd unlessotherwisespeci ? ed. table6.1absolutemaximumratings parameterrangeunits v dd supplyvoltage 0.3vto+4.0vv allinputsandoutputs 0.3vto5.5vv packagepowerdissipation2.0@70 ? cw storagetemperature 65to+150 ? c temperatureunderbias 10to+80 ? c commercialtemperature-10to+80 ? c industrialtemperature-40to+85 ? c leadtemperature(soldering,10sec)260 ? c bodytemperature(soldering,30sec)220 ? c 6-2speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.2electricalcharacteristics table6.2 liststhedevicedcelectricalcharacteristics.unlessotherwise noted,alltestconditionsareasfollows: ta=0to+70 ? c(commercial),-40to+85 ? c(industrial) v dd =3.3v 5% clock=25mhz+0.01% rext=10k +1%,noload table6.2dccharacteristics symparameter limit unitconditions mintypmax vilinputlowvoltage0.8voltallexceptoscin,mda[3:0]n v dd 1.0voltmda[3:0]n 1.5voltoscin vihinputhighvoltage25.5voltallexceptoscin,mda[3:0]n v dd 200mvmda[3:0]n 2.3voltoscin iilinputlowcurrent 1 avin=gnd.allexceptoscin, mda[3:0]n,resetn 4 25 avin=gnd.mda[3:0]n 12 120 avin=gnd.resetn 150 avin=gnd.oscin iihinputhighcurrent1 avin=v dd .allexceptoscin 150 avin=v dd .oscin voloutputlow voltage 0.4voltiol= 4ma.allexcept pled[5:0]n 1voltiol= 10ma.pled[5:0]n electricalcharacteristics6-3 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.2.1twisted-pairdccharacteristics unlessotherwisenoted,alltestconditionsfortptransmitandreceive operationsareasfollows: ta=0to+70 ? c(commercial),-40to+85 ? c(industrial) v dd =3.3v 5% clock=25mhz .01% rext=10k %,noload tpo+/-loadingisasshownin figurea.1 orequivalent 62.5/10mhzsquarewaveontp+/-inputsin100/10mbits/smodes table6.3 showsthetwisted-paircharacteristicsfortransmitoperation. vohoutputhigh voltage v dd 1.0voltioh=4ma.allexcept pled[5:0]n 2.4voltioh=4 a.pled[5:2]n v dd 1.0voltioh=10ma.pled[1:0]n cininputcapacitance5pf iddv dd supply current 120matransmitting,100mbits/s 140matransmitting,10mbits/s igndgndsupply current 190matransmitting,100mbits/s 1 , note1 220matransmitting,10mbits/s 1 ipdnpowerdown supplycurrent 200 apowerdown,eitheriddor ignd 1.igndincludescurrent ? owingintogndfromtheexternalresistorsandtransformerontpoas shownin figurea.1 table6.2dccharacteristics(cont.) symparameter limit unitconditions mintypmax 6-4speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. table6.3twistedpaircharacteristics(transmit) symparameter limit unitconditions mintypmax t ov tpdifferentialoutput voltage 0.9501.0001.050vpk100mbits/s,utpmode,100ohm load 2.22.52.8vpk10mbits/s,utpmode,100ohm load t ovs tpdifferentialoutput voltagesymmetry 98102%100mbits/s,ratioofpositiveand negativeamplitudepeakson tpo t orf tpdifferentialoutput riseandfalltime 3.05.0ns100mbits/s t orfs tpdifferentialoutput riseandfalltime symmetry 0.5ns100mbits/s,differencebetween riseandfalltimesontpo t odc tpdifferentialoutput dutycycledistortion 0.25ns100mbits/s,outputdata= 0b0101...nrzpattern unscrambled,measureat50% points t oj tpdifferentialoutput jitter 1.4ns100mbits/s,outputdata= scrambled/h/ t oo tpdifferentialoutput overshoot 5.0%100mbits/s t ovt tpdifferentialoutput voltagetemplate see figure2.4 10mbits/s t soi tpdifferentialoutput soivoltagetemplate see figure2.6 10mbits/s t lpt tpdifferentialoutput linkpulsevoltage template see figure2.7 10mbits/s,nlpandflp t oiv tpdifferentialoutput idlevoltage 50mv10mbits/s.measuredon secondarysideoftransformerin figurea.1 . t oia tpoutputcurrent384042mapk100mbits/s 88100112mapk10mbits/s t oir tpoutputcurrent adjustmentrange 0.801.2v dd =3.3v,adjustablewith rext,relativetotoiawith rext=10k t or tpoutputresistance10kohm t oc tpoutputcapacitance15pf electricalcharacteristics6-5 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. table6.4 showsthetwisted-paircharacteristicsforreceiveoperation. table6.4twistedpaircharacteristics(receive) symparameter limit unitconditions mintypmax r st tpinputsquelch threshold 166500mvpk100mbits/s,rlvl=0 310540mvpk10mbits/s,rlvl=0 r ut tpinputunsquelch threshold 100300mvpk100mbits/s,rlvl=0 186324mvpk10mbits/s,rlvl=0 r ocv tpinputopencircuit voltage v dd 2.4 0.2 voltvoltageoneithertpi+or tpi withrespecttognd. r cmr tpinputcommon- modevoltagerange r ocv 0.25voltageontpi withrespect tognd. r dr tpinputdifferential voltagerange v dd volt r ir tpinputresistance5kohm r ic tpinputcapacitance10pf 6-6speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.3acelectricalcharacteristics unlessotherwisenoted,alltestconditionsareasshownin table6.5 . table6.5testconditions testconditionparametervalue temperature(commercial)ta0to+70c temperature(industrial)ta-40to+85c voltagev dd 3.3v 5% clockfrequency25mhz0.01% externalresistorrext10k1%,noload inputconditions(allinputs)tr,tf 10ns,20-80%points outputloading tposameas figurea.1 or equivalent 10pf open-drainoutputs1kpullup,50pf allotherdigitaloutputs25pf measurementpoints tpo,tpi0.0vduringdata,0.3vatstart/endofpacket allotherinputsandoutputs1.4v acelectricalcharacteristics6-7 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.3.125mhzinput/outputclocktimingcharacteristics table6.6 showsthe25mhzinput/outputclocktimingparameters.see figure6.1 forthetimingdiagram. figure6.125mhzoutputtiming 6.3.2transmittimingcharacteristics table6.7 showsthetransmitactimingparameters.see figure6.2and figure6.3 forthe100mbits/sand10mbits/stransmittimingdiagrams. table6.625mhzinput/outputclock symparameter limit unitconditions mintypmax t1oscinperiod39.9964040.004nsclockappliedtooscin t2oscinhightime16nsclockappliedtooscin t3oscinlowtime16nsclockappliedtooscin t4oscintotx_clk delay 10ns100mbits/s 20ns10mbits/s oscin t 1 t 2 t 3 tx_clk (100 mbits/s) t 4 t 4 t 4 tx_clk (10 mbits/s) 6-8speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. table6.7transmittiming symparameter limit unitconditions mintypmax t11tx_clkperiod39.9964040.004ns100mbits/s 399.96400400.04ns10mbits/s t12tx_clklowtime162024ns100mbits/s 160200240ns10mbits/s t13tx_clkhightime162024ns100mbits/s 160200240ns10mbits/s t14tx_clkrise/falltime10ns t15tx_ensetuptime15nsnote 1 1.setuptimemeasuredwith5pfloadingontxc.additionalleadingwillcreatedelayontxcrise timewhichwillrequireincreasedsetuptimes. t16tx_enholdtime0ns t17crsduringtransmitasserttime40ns100mbits/s 400ns10mbits/s t18crsduringtransmitdeassert time 160ns100mbits/s 900ns10mbits/s t19txdsetuptime15nsnote1 t20txdholdtime0ns t21tx_ersetuptime15nsnote1 t22tx_erholdtime0ns t23transmitpropagationdelay60140ns100mbits/s,mii 600ns10mbits/s t24transmitoutputjitter 0.7nspk-pk100mbits/s 5.5nspk-pk10mbits/s t25transmitsoipulsewidthto0.3v250ns10mbits/s t26transmitsoipulsewidthto40mv4500ns10mbits/s t27pledndelaytime25msplednprogrammed foractivity t28plednpulsewidth80105msplednprogrammed foractivity acelectricalcharacteristics6-9 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.2transmittiming(100mbits/s) n1 tx_clk tx_en txd[3:0] tpo n0n2 t 15 t 19 t 27 t 28 t 11 t 16 pledn idle idle /j/k/ data/t/r/idle t 23 t 24 crs t 13 t 12 t 14 t 14 t 18 t 17 n3 t 20 t 22 t 21 tx_er mi 100 mbits/s fxo 6-10speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.3transmittiming(10mbits/s) preamble preamble data soi data n1 tx_clk tx_en txd[3:0] tp0 n0n2 t 15 t 19 t 27 t 28 t 11 t 16 pledn t 23 crs t 13 t 12 t 14 t 14 t 18 t 17 n3 t 20 t 24 t 26 t 25 mi 10 mbits/s acelectricalcharacteristics6-11 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.3.3receivetimingcharacteristics table6.8 showsthereceiveactimingparameters.see figure6.4 through figure6.8 forthereceivetimingdiagrams. table6.8receivetiming symparameter limit unitconditions mintypmax t31startofpacketto crsassertdelay 200ns100mbits/s,mii 700ns10mbits/s t32endofpacketto crsdeassert delay 130240ns100mbits/s,mii 600ns10mbits/s.relativetostart ofsoipulse t33startofpacketto rx_dvassert delay 240ns100mbits/s 3600ns10mbits/s t34endofpacketto rx_dvdeassert delay 280ns100mbits/s 1000ns10mbits/s.relativetostart ofsoipulse t37rx_clkto rx_dv,rxd, rx_erdelay 88ns100mbits/s 8080ns10mbits/s t38rx_clkhigh time 182022ns100mbits/s 180200600ns10mbits/s t39rx_clklowtime182022ns100mbits/s 180200600ns10mbits/s t40soipulse minimumwidth requiredforidle detection 125200ns10mbits/smeasuretpi fromlastzerocrossto 0.3vpoint. 6-12speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. t41receiveinputjitter 3.0nspk pk100mbits/s 13.5nspk-pk10mbits/s t43pledndelaytime25msplednprogrammedfor activity t44plednpulse width 80105msplednprogrammedfor activity t45rx_clk,rxd, crc,rx_dv, rx_eroutput riseandfall times 10ns t46rx_endeassert torcvmiioutput hi-zdelay 40ns t47rx_enassertto rcvmiioutput activedelay 40ns table6.8receivetiming(cont.) symparameter limit unitconditions mintypmax acelectricalcharacteristics6-13 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.4receivetiming,startofpacket(100mbits/s) figure6.5receivetiming,endofpacket(100mbits/s) txtxtxtxtxrxrxrxrxrxrx t 37 idlej datadatadatadatadatadatadatadatadatadatadata tpi crs rx_clk rx_dv rxd[3:0] datadatadata kdata datadatadata t 31 t 41 preamble preamble preamble preamble preamble rx_er pledn t 38 t 39 t 37 t 37 t 37 t 43 t 44 t 33 mi 100 mbits/s rx rxrxrxrxrxrxrxtxtx t 38 datat tpi crs rx_clk rxd[3:0] r i t 32 iiiiiiiiiiiiiiiiii data data data data data data data mi 100 mbits/s t 39 t 34 t 37 rx_dv fxi 6-14speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.6receivetiming,startofpacket(10mbits/s) rxrxrx rx rxrx tx tx tx tx tx data tpi crs rx_clk rxd[3:0] data t 37 data data t 41 t 31 data preamble t 43 rx_er t 44 preamble t 38 t 39 t 33 pledn rx_dv t 37 mi 10 mbits/s acelectricalcharacteristics6-15 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.7receivetiming,endofpacket(10mbits/s) figure6.8rx_entiming tpi crs rx_clk rx_dv data t 41 data soi t 32 t 40 t 38 t 37 data data data data data data rx rxd[3:0] rxrxrxrxrxrxrxtxtx t 39 t 34 data data data data mi 10 mbits/s rx_en rx_clk rxd[3:0] rx_dv rx_er col t 47 t 46 6-16speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.3.4collisionandjamtimingcharacteristics table6.9 showsthecollisionandjamtimingparameters.see figure6.9 through figure6.13 fortheassociatedtimingdiagrams. table6.9collisionandjamtiming symparameter limit conditions mintypmaxunit t51rcvpacketstartto colasserttime 200ns100mbits/s 700ns10mbits/s t52rcvpacketstopto coldeasserttime 130240ns100mbits/s 300ns10mbits/s t53xmtpacketstartto colasserttime 200ns100mbits/s 700ns10mbits/s t54xmtpacketstopto coldeasserttime 240ns100mbits/s 300ns10mbits/s t55pledndelaytime25msplednprogrammedforcollision t56plednpulsewidth80105msplednprogrammedforcollision t57collisiontestassert time 5120ns t58collisiontest deasserttime 40ns t59 1 1.timingnotshown crsassertto transmitjampacket startduringjam 300ns100mbits/s 800ns10mbits/s t60 1 colriseandfall time 10ns acelectricalcharacteristics6-17 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.9collisiontiming,receive(100mbits/s) figure6.10collisiontiming,receive(10mbits/s) tpo tpi col pledn mi 100 mbits/s i data data data data data data data data data data data data data i i i i j k data data data data t r i i t 51 t 52 t 56 t 55 fxo mi 10 mbits/s t 51 t 52 t 55 t 56 tpo tpi col pledn 6-18speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.11collisiontiming,transmit(100mbits/s) figure6.12collisiontiming,transmit(10mbits/s) figure6.13collisiontesttiming tpo tpi col pledn mi 100 mbits/s i data data data data data data data data data data data data data i i i i j k data data data data t r i i t 53 t 54 t 56 t 55 fxo fxi mi 10 mbits/s t 53 t 54 t 55 t 56 tpi tpo col pledn col tx_en t 58 t 57 acelectricalcharacteristics6-19 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.3.5linkpulsetimingcharacteristics table6.10 showsthelinkpulseactimingparameters.see figure6.14 and figure6.15 forthelinkpulsetimingdiagrams. table6.10linkpulsetiming symparameter limit unitcondition mintypmax t61nlptransmitlinkpulse width see figure2.7 ns t62nlptransmitlinkpulse period 824ms t63nlpreceivelinkpulse widthrequiredfordetection 50ns t64nlpreceivelinkpulse minimumperiodrequired fordetection 67mslink_test_min t65nlpreceivelinkpulse maximumperiodrequired fordetection 50150mslink_test_max t66nlpreceivelinkpulses requiredtoexitlinkfail state 333link pulses lc_max t67flptransmitlinkpulse width 100150ns t68flptransmitclockpulseto datapulseperiod 55.562.569.5msinterval_timer t69flptransmitclockpulseto clockpulseperiod 111125139ms t70flptransmitlinkpulse burstperiod 822mstransmit_link_burst _timer t71flpreceivelinkpulse widthrequiredfordetection 50ns t72flpreceivelinkpulse minimumperiodrequired forclockpulsedetection 525ms ? p_test_min_timer 6-20speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. t73flpreceivelinkpulse maximumperiodrequired forclockpulsedetection 165185ms ? p_test_max_timer t74flpreceivelinkpulse minimumperiodrequired fordatapulsedetection 1547msdata_detect_min_ timer t75flpreceivelinkpulse maximumperiodrequired fordatapulsedetection 78100msdata_detect_max_ timer t76flpreceivelinkpulses requiredtodetectvalid flpburst 1717link pulses t77flpreceivelinkpulse burstminimumperiod requiredfordetection 57msnlp_test_min_timer t78flpreceivelinkpulse burstmaximumperiod requiredfordetection 50150msnlp_test_max_ timer t79flpreceivelinkpulses burstsrequiredtodetect autonegotiationcapability 333link pulse t80flpreceiveacknowledge failperiod 12001500ms t81flptransmitrenegotiate linkfailperiod 12001500msbreak_link_timer t82nlpreceivelinkpulse maximumperiodrequired fordetectionafterflp negotiationhascompleted 7501000mslink_fail_inhibit_ timer table6.10linkpulsetiming(cont.) symparameter limit unitcondition mintypmax acelectricalcharacteristics6-21 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. t73flpreceivelinkpulse maximumperiodrequired forclockpulsedetection 165185ms ? p_test_max_timer t74flpreceivelinkpulse minimumperiodrequired fordatapulsedetection 1547msdata_detect_min_ timer t75flpreceivelinkpulse maximumperiodrequired fordatapulsedetection 78100msdata_detect_max_ timer t76flpreceivelinkpulses requiredtodetectvalid flpburst 1717link pulses t77flpreceivelinkpulse burstminimumperiod requiredfordetection 57msnlp_test_min_timer t78flpreceivelinkpulse burstmaximumperiod requiredfordetection 50150msnlp_test_max_ timer t79flpreceivelinkpulses burstsrequiredtodetect autonegotiationcapability 333link pulse t80flpreceiveacknowledge failperiod 12001500ms t81flptransmitrenegotiate linkfailperiod 12001500msbreak_link_timer t82nlpreceivelinkpulse maximumperiodrequired fordetectionafterflp negotiationhascompleted 7501000mslink_fail_inhibit_ timer table6.10linkpulsetiming(cont.) symparameter limit unitcondition mintypmax 6-22speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. t73flpreceivelinkpulse maximumperiodrequired forclockpulsedetection 165185ms ? p_test_max_timer t74flpreceivelinkpulse minimumperiodrequired fordatapulsedetection 1547msdata_detect_min_ timer t75flpreceivelinkpulse maximumperiodrequired fordatapulsedetection 78100msdata_detect_max_ timer t76flpreceivelinkpulses requiredtodetectvalid flpburst 1717link pulses t77flpreceivelinkpulse burstminimumperiod requiredfordetection 57msnlp_test_min_timer t78flpreceivelinkpulse burstmaximumperiod requiredfordetection 50150msnlp_test_max_ timer t79flpreceivelinkpulses burstsrequiredtodetect autonegotiationcapability 333link pulse t80flpreceiveacknowledge failperiod 12001500ms t81flptransmitrenegotiate linkfailperiod 12001500msbreak_link_timer t82nlpreceivelinkpulse maximumperiodrequired fordetectionafterflp negotiationhascompleted 7501000mslink_fail_inhibit_ timer table6.10linkpulsetiming(cont.) symparameter limit unitcondition mintypmax acelectricalcharacteristics6-23 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.14nlplinkpulsetiming tpo tpi pledn a. transmit nlp b. receive nlp t 61 t 64 t 63 t 65 t 66 t 62 6-24speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figure6.15flplinkpulsetiming tpi t 78 t 77 t 79 ledn a. transmit flp and transmit flp burst clkdataclkdataclkdata clk tpo t 68 t 69 t 67 t 70 clkdataclkdata t 73 t 71 31.2562.50125.00156.25 t 74 t 75 tpi b. receive flp c. receive flp burst 93.75 t 72 acelectricalcharacteristics6-25 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.3.6jabbertimingcharacteristics table6.11 showsthejabberactimingparameters.see figure6.16 for thejabbertimingdiagram. figure6.16jabbertiming table6.11jabbertiming symparameter limit unitconditions mintypmax t91jabberactivationdelaytime50100ms10mbits/s t92jabberdeactivationdelaytime250750ms10mbits/s tpo txen crs col t 91 t 92 t 91 t 91 mi 100 mbits/s mi 10 mbits/s not applicable 6-26speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.3.7miserialporttimingcharacteristics table6.12 showsthemiserialportactimingparameters.see figure6.17 fortheassociatedtimingdiagram. figure6.17miserialporttiming table6.12miserialporttiming symparameter limit unitconditions mintypmax t101mdchightime20ns t102mdclowtime20ns t103mdiosetuptime10nswritebits t104mdioholdtime10nswritebits t105mdctomdiodelay20nsreadbits t106mdiohi-ztoactivedelay20nswrite-readbit transition t107mdioactivetohi-zdelay20nsread-writebit transition t108framedelimiter(idle)32clocksnumberof consecutivemdc clockswithmdio=1 mdio mdc (read) mdio (write) 0 st1st0 regad0 ta1ta0d15 d1d0 113141516173031 t 103 t 104 t 103 t 106 ta1 t 105 t 107 t 104 st1st0 regad0 ta0d15d14d0 t 101 t 102 pinoutsandpackagedrawings6-27 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.4pinoutsandpackagedrawings thissectioncontainsthealphabeticalandnumericalpinlistingsforthe L80227aswellasitspinoutsandpackagedrawing. 6.4.1L80227pinouts table6.13 and table6.14 containthelistofL80227signals.the ? rst tableliststhesignalsbycategoryandthesecondliststhembypin number. table6.13L80227pinlist(bysignalcategory) pinnamepinnumberdescription mediainterface rext50transmitcurrentset tpi-59twistedpairreceiveinput,negative tpi+58twistedpairreceiveinput,positive tpo-55twistedpairtransmitoutput,negative tpo+54twistedpairtransmitoutput,positive controllerinterface crs13carriersenseoutput oscin42clockoscillatorinput rx_clk26receiveclockoutput rx_dv14receivedatavalidoutput rx_en27receiveenableinput rx_er18receiveerroroutput rxd022receivedataoutput rxd121receivedataoutput rxd220receivedataoutput rxd319receivedataoutput tx_clk34transmitclockoutput tx_en40transmitenableinput tx_er39transmiterrorinput 6-28speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. txd035transmitdatainput txd136transmitdatainput txd237transmitdatainput txd338transmitdatainput managementinterface(mi) mdc10managementinterface(mi)clockinput mda4n9managementinterfaceaddressinput mdio11managementinterface(mi)datainput/output pled0n/mda0n61programmableledoutput/managementinterfaceaddressinput pled1n/mda1n62programmableledoutput/managementinterfaceaddressinput pled2n/mda2n3programmableledoutput/managementinterfaceaddressinput pled3n/mda3n4programmableledoutput/managementinterfaceaddressinput leds pled4n2transmitledoutput pled5n63receiveledoutput miscellaneous aneg30autonegotiationcontrolinput col12collisionoutput dplx29full/half-duplexselectinput speed28speedselectinput nc1noconnect nc5noconnect nc15noconnect nc16noconnect nc17noconnect nc24noconnect nc33noconnect nc43noconnect table6.13L80227pinlist(bysignalcategory)(cont.) pinnamepinnumberdescription pinoutsandpackagedrawings6-29 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. nc45noconnect nc46noconnect nc47noconnect nc48noconnect nc49noconnect nc51noconnect nc64noconnect resetn44resetinput power v dd 156positivesupply.3.3v 5%volts v dd 257positivesupply.3.3v 5%volts v dd 37positivesupply.3.3v 5%volts v dd 48positivesupply.3.3v 5%volts v dd 525positivesupply.3.3v 5%volts v dd 632positivesupply.3.3v 5%volts ground gnd152ground gnd260ground gnd36ground gnd441ground gnd523ground gnd631ground gnd753ground table6.13L80227pinlist(bysignalcategory)(cont.) pinnamepinnumberdescription 6-30speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. . table6.14L80227pinlist(bypinnumber) pin numberpinnamedescription 1ncnoconnect 2pled4ntransmitledoutput 3pled2n/mda2nprogrammableledoutput/managementinterfaceaddressinput 4pled3n/mda3nprogrammableledoutput/managementinterfaceaddressinput 5ncnoconnect 6gnd3ground 7v dd 3positivesupply.3.3v 5%volts 8v dd 4positivesupply.3.3v 5%volts 9mda4nmanagementinterfaceaddressinput 10mdcmanagementinterface(mi)clockinput 11mdiomanagementinterface(mi)datainput/output 12colcollisionoutput 13crscarriersenseoutput 14rx_dvreceivedatavalidoutput 15ncnoconnect 16ncnoconnect 17ncnoconnect 18rx_erreceiveerroroutput 19rxd3receivedataoutput 20rxd2receivedataoutput 21rxd1receivedataoutput 22rxd0receivedataoutput 23gnd5ground 24ncnoconnect pinoutsandpackagedrawings6-31 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 25v dd 5positivesupply.3.3v 5%volts 26rx_clkreceiveclockoutput 27rx_enreceiveenableinput 28speedspeedselectinput 29dplxfull/half-duplexselectinput 30anegautonegotiationcontrolinput 31gnd6ground0volts 32v dd 6positivesupply.3.3v 5%volts 33ncnoconnect 34tx_clktransmitclockoutput 35txd0transmitdatainput 36txd1transmitdatainput 37txd2transmitdatainput 38txd3transmitdatainput 39tx_ertransmiterrorinput 40tx_entransmitenableinput 41gnd4ground 42oscinclockoscillatorinput 43ncnoconnect 44resetnresetinput 45ncnoconnect 46ncnoconnect 47ncnoconnect 48ncnoconnect 49ncnoconnect table6.14L80227pinlist(bypinnumber)(cont.) pin numberpinnamedescription 6-32speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 50rexttransmitcurrentset 51ncnoconnect 52gnd1ground 53gnd7ground 54tpo+twistedpairtransmitoutput,positive 55tpo-twistedpairtransmitoutput,negative 56v dd 1positivesupply.3.3v 5%volts 57v dd 2positivesupply.3.3v 5%volts 58tpi+twistedpairreceiveinput,positive 59tpi-twistedpairreceiveinput,negative 60gnd2ground 61pled0n/mda0nprogrammableledoutput/managementinterfaceaddressinput 62pled1n/mda1nprogrammableledoutput/managementinterfaceaddressinput 63pled5nreceiveledoutput 64ncnoconnect table6.14L80227pinlist(bypinnumber)(cont.) pin numberpinnamedescription pinoutsandpackagedrawings6-33 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.4.2L80227pinlayout figure6.18 showsthepinlayoutfortheL80227package. figure6.18L8022764-pinlqfp,topview L80227 64-pin lqfp top view nc pled4n pled2n/mda2n pled3n/mda3n nc gnd3 v dd 3 v dd 4 mda4n mdc mdio col crs rx_dv nc nc n c r x _ e r r x d 3 r x d 2 r x d 1 r x d 0 g n d 5 n c v d d 5 r x _ c l k r x _ e n s p e e d d p l x a n e g g n d 6 v d d 6 nc nc nc nc resetn nc oscin gnd4 tx_en tx_er txd3 txd2 txd1 txd0 tx_clk nc n c p l e d 5 n p l e d 1 n / m d a 1 n p l e d 0 n / m d a 0 n g n d 2 t p i t p i v d d 2 v d d 1 t p o t p o g n d 7 g n d 1 n c r e x t n c 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1. nc pinsarenotconnected. 6-34speci ? cations copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. 6.5mechanicaldrawing thissectioncontainsthemechanicaldrawingfortheL8022764-pin lqfppackage. figure6.1964-pinlqfppackagedrawing notes 1. all dimensions are in millimeters. 2. dimensions do not include mold flash. maximum allowable flash is 0.25. 3. all leads are coplanar to a tolerance of 0.08 (ccc). bent leads to a tolerance of 0.08 (ddd). symboldimensions b0.17 - 0.27 e0.50 basic cccmax. 0.08 dddmax. 0.08 d11.85 - 12.15 e11.85 - 12.15 l0.45 - 0.75 l11.0 ref r0.08 - 0.20 r1min. 0.08 amax. 1.60 a10.05 - 0.15 a21.292 - 1.508 c0.09 - 0.20 d19.90 - 10.10 e19.90 - 10.10 @0 - 7 @1min. 0 @212 dimension table b e d e a e1 d1 see detail a see detail b b detail b c pin 1 @ l a1 r1 r detail a a2 a l1 @1 @2 ccc ddd lsi L80227 L8022710base-t/100base-txethernetphytechnicalmanuala-1 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. appendixa applicationinformation thisappendixcontainsapplicationinformationforthedevice.itcontains thefollowingsections: sectiona.1, exampleschematics sectiona.2, tptransmitinterface sectiona.3, tpreceiveinterface sectiona.4, tptransmitoutputcurrentset sectiona.5, transmitterdroop sectiona.6, miicontrollerinterface sectiona.7, repeaterapplications sectiona.8, serialport sectiona.9, oscillator sectiona.10, leddrivers sectiona.11, powersupplydecoupling a.1exampleschematics atypicalexampleschematicoftheL80227usedinannetworkinterface adaptercardapplicationisshownin figurea.1 ;atypicalswitchingport applicationisshownin figurea.2 ;andanexternalphyapplicationis shownin figurea.3 . a-2applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figurea.1typicalnetworkinterfaceadaptercardschematicusingtheL80227 gnd [6:1] tx_clk tx_d3 tx_d2 tx_d1 tx_d0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio pled[5:0]n oscin vdd [4:1] bus interface 6 rext 10 k tpi tpi 1 2 4 5 7 8 3 6 rj45 75 75 1:1 0.01 tpo tpo 50 1% 50 1% lsi l80c300 or equivalent 10/100 mbits/s ethernet L80227 controller system bus 2 kv 75 1:1 25 1% 25 1% 0.01 25 1% 75 1% resetn to system reset or float led 500 6x optional 25 mhz 25 1% rx_en optional system clock exampleschematicsa-3 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figurea.2typicalswitchingportschematicusingL80227 vdd [4:1] gnd [6:1] switch fabric rext 10 k tpi tpi 1 2 4 5 7 8 3 6 rj45 75 75 1:1 0.01 tpo tpo 50 1% 50 1% lsi l84302 tx_clk txd3 txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio rx_en L80227 2 kv 75 1:1 25 1% 25 1% 0.01 25 1% 75 1% optional resetn to system reset or float 25 1% oscin 25 mhz system clock pled[5:2]n pled[1:0]n 2 led 500 2x optional 4 led 500 4x optional or equivalent 50k 10/100 mbits/s ethernet controller a-4applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figurea.3typicalexternalphyschematicusingL80227 vdd [4:1] gnd [6:1] 6 rext 10 k tpi tpi 1 2 4 5 7 8 3 6 rj45 75 75 1:1 0.01 tpo tpo 50 1% 24.9 1% mii connectors tx_clk txd3 txd2 txd1 txd0 tx_en tx_er col rx_clk rxd3 rxd2 rxd1 rxd0 crs rx_dv rx_er mdc mdio rx_en L80227 2 kv 75 1:1 25 1% 25 1% 0.01 25 1% 75 1% optional resetn led 500 6x optional pled[5:0]n oscin 25 1% 50 1% 1.5 k 5% optional 25 mhz system clock tptransmitinterfacea-5 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. a.2tptransmitinterface theinterfacebetweenthetpoutputsontpo andthetwistedpair cableistypicallytransformercoupledandterminatedwiththetwo resistorsasshownin figurea.1 through figurea.3 . thetransformerforthetransmittershouldhaveawindingratioof1:1with acentertapontheprimarywindingtiedtov dd ,asshownin figurea.1 through figurea.3 .thespeci ? cationsforthetransformerareshownin tablea.1 .sourcesforthetransformerarelistedin tablea.2 . thetransmitoutputmustbeterminatedwithtwoexternaltermination resistorstomeettheoutputimpedanceandreturnlossrequirementsof tablea.1tptransformerspeci ? cation parameter speci ? cation transmitreceive turnsratio1:1ct1:1 inductance,(hmin)350350 leakageinductance,(h)0.05 C 0.150.0 C 0.2 capacitance(pfmax)1515 dcresistance( max)0.40.4 tablea.2tptransformersources 1 1.h1089,s558-5999-46,epf8017ghandtg22-3506ndarepincompatible. pleasecontactthetransformervendorforadditionalinformation. vendorpartnumber pulseh1089,h1102 bels558-5999-j9,558-5999-46 halotg22-3506ndtg110-s050n2 pcaepf8017gh midcommod2 tm technology0510 2 2.rj-45connectorwithintegratedmagneticsandleds a-6applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. ieee802.3.thesetwoexternalresistorsmustbeconnectedbetween v dd andeachofthetpo outputs.theirvalueshouldbechosento providethecorrectterminationimpedancewhenlookingbackthrough thetransformerfromthetwisted-paircable,asshownin figurea.1 through figurea.3 .thevalueofthesetwoexternalterminationresistors dependsonthetypeofcablethedevicedrives. tominimizecommon-modeoutputnoiseandtoaidinmeetingradiated emissionsrequirements,itmaybenecessarytoaddacommon-mode chokeonthetransmitoutputsaswellasaddcommon-modebundle termination.thequali ? edtransformersmentionedin tablea.2 allcontain common-modechokesalongwiththetransformersonboththetransmit andreceivesides,asshownin figurea.1 through figurea.3 .common- modebundleterminationmaybeneededandcanbeachievedwhenthe unusedpairsintherj45connectorareconnectedtochassisground through75ohmresistorsanda0.01 fcapacitor,asshownin figurea.1 through figurea.3 . tominimizenoisepickupintothetransmitpathinasystemoronapcb, theloadingontpo shouldbeminimized,andbothoutputsshould alwaysbeloadedequally. a.3tpreceiveinterface receivedataistypicallytransformercoupledintothereceiveinputson tpi andterminatedwithexternalresistorsasshownin figurea.1 through figurea.3 . thetransformerforthereceivershouldhaveawindingratioof1:1,as shownin figurea.1 through figurea.3 .thespeci ? cationsforthis transformerareshownin tablea.1 andsourcesforthetransformerare listedin tablea.2 . thereceiveinputmustbeterminatedwiththecorrecttermination impedancetomeettheinputimpedanceandreturnlossrequirementsof ieee802.3.inaddition,thereceivetpinputsmustbeattenuated.both theterminationandattenuationisaccomplishedwithfourexternal resistorsinseriesacrossthetpi inputs,asshownin figurea.1 through figurea.3 .eachresistorshouldbe25%ofthetotalseriesresistance, andthetotalseriesresistanceshouldbeequaltothecharacteristic impedanceofthecable(100ohmforutp).itisalsorecommendedthat tptransmitoutputcurrentseta-7 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. a0.01fcapacitorbeplacedbetweenthecenteroftheseriesresistor stringandv dd toprovideanacgroundforattenuatingcommon-mode signalattheinput.thiscapacitorisalsoshownin figurea.1 through figurea.3 . tominimizecommon-modeinputnoiseandtoaidinmeeting susceptibilityrequirements,itmaybenecessarytoaddacommon-mode chokeonthereceiveinputaswellasaddcommon-modebundle termination.thequali ? edtransformersmentionedin tablea.2 allcontain common-modechokesalongwiththetransformersonboththetransmit andreceivesides,asshownin figurea.1 through figurea.3 .common- modebundleterminationmaybeneededandcanbeachievedwhenthe receivesecondarycentertapandtheunusedpairsintherj45 connectorareconnectedtochassisgroundthrough75-ohmresistors anda0.01fcapacitor,asshownin figurea.1 through figurea.3 . tominimizenoisepickupintothereceivepathinasystemoronapcb, loadingontpi+/ shouldbeminimizedandbothinputsshouldbeloaded equally. a.4tptransmitoutputcurrentset thetpo outputcurrentlevelissetwithanexternalresistorconnected betweentherextpinandgnd.thisoutputcurrentisdeterminedfrom thefollowingequation,whereristhevalueofrext: i out =(10k/r)i ref where rextshouldtypicallybea10k 1%resistortomeetieee802.3 speci ? edlevels.oncerextissetforthe100mb its/ sandutpmodes asshownbytheequationabove,i ref isthenautomaticallychangedinside ir ef =40ma(100mbits/s,utp) =32.6ma(100mbits/s,stp) =100ma(10mbits/s,utp) =81.6ma(10mbits/s,stp) a-8applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. thedevicewhenthe10mb its/ smodeorutp120/stp150modesare selected. keeprextasclosetotherextandgndpinsaspossibletoreduce noisepickupintothetransmitter. becausethetpoutputisacurrentsource,capacitiveandinductive loadingcanreducetheoutputvoltagefromtheideallevel.thus,inactual application,itmightbenecessarytoadjustthevalueoftheoutput currenttocompensateforexternalloading.onewaytoadjustthetp outputlevelistochangethevalueoftheexternalresistorconnectedto rext. a.5transmitterdroop theieee802.3speci ? cationhasatransmitoutputdrooprequirementfor 100base-tx.becausetheL80227tpoutputisacurrentsource,ithas noperceptibledroopbyitself.however,theinductanceofthetransformer addedtothedevicetransmitteroutputasshownin figurea.1 through figurea.3 causesdrooptoappearatthetransmitinterfacetothetp wire.ifthetransformerconnectedtotheL80227outputsmeetsthe requirementsof tablea.1 ,thetransmitinterfacetothetpcablethen meetstheieee802.3drooprequirements. a.6miicontrollerinterface themiicontrollerinterfaceallowstheL80227toconnecttoanyexternal ethernetcontrollerwithoutanygluelogic,providedtheexternalethernet controllerhasanmiiinterfacethatcomplieswithieee802.3,asshown in figurea.1 through figurea.3 . a.6.1clocks standardethernetcontrollerswithanmiiusetx_clktoclockdatain ontxd[3:0].tx_clkisspeci ? edinieee802.3andontheL80227to beanoutput.ifanonstandardcontrollerorotherdigitaldeviceisused tointerfacetotheL80227,theremightbeaneedtoclocktxd[3:0]into theL80227ontheedgesofanexternalmasterclock.themasterclock, inthiscase,wouldbeaninputtotheL80227.todothis,useoscinas miicontrollerinterfacea-9 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. themasterclockinput.becauseoscingeneratestx_clkinsidethe L80227,dataontxd[3:0]canbeclockedintotheL80227onedgesof outputclocktx_clkorinputclockoscin.inthecasewhereoscinis usedastheinputclock,acrystalisnolongerneededonoscin,and tx_clkcanbeleftopenorusedforsomeotherpurpose. a.6.2outputdrive thedigitaloutputsontheL80227controllersignalsmeetthemiidriver characteristicsspeci ? edinieee802.3andshownin figurea.4 if external24.9 1%terminationresistorsareadded.thesetermination resistorsareonlyneedediftheoutputsmustdriveanmiicableorother transmissionlinetypeload,suchasintheexternalphyapplication shownin figurea.3 .iftheL80227isusedinembeddedapplications, suchasadaptercardsandswitchinghubs(see figurea.1 and figurea.2 ),theseterminationsresistorsarenotneeded. a-10applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. figurea.4miioutputdrivercharacteristics a.6.3miidisable settingthemiidisablebit(mii_dis)inthemiserialportcontrolregister placesthemiioutputsinthehigh-impedancestateandthedisablesthe miiinputs.whenthisbitissettothedisablestate,thetpoutputsare alsodisabledandtransmissionisinhibited.thedefaultvalueofthisbit whenthedevicepowersuporisresetisdependentonthephysical deviceaddress.ifthedeviceaddresslatchedintomda[3:0]natresetis 0b1111,itisassumedthatthedeviceisbeingusedinapplicationswhere theremaybemorethanonedevicesharingthemiibus,suchasinthe useofexternalphysoradaptercards.inthiscase,thedevicepowers upwiththemiiinterfacedisabled.ifthedeviceaddresslatchedinto mda[3:0]natresetisnot0b1111,itisassumedthatthedeviceisbeing usedinapplicationwhereitistheonlydeviceonthemiibus,suchasin theuseofhubs,sothedevicepowersupwiththemiiinterfaceenabled. vohvol loh lol rol min = 40 ohm v 3 i 3 v 4 i 4 v 2 i 2 v 1 i 1 v dd rol min = 40 ohm i C v i 1 , C v 1 i 2 , C v 2 i 3 , C v 3 i 4 , C v 4 i (ma) 20 4 4 43 v (volts) 1.10 2.40 0.40 3.05 repeaterapplicationsa-11 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. a.6.4receiveoutputenable thereceiveoutputenablepin,rx_en,forcesthereceiveandcollision miioutputsintothehigh-impedancestate.morespeci ? cally,when rx_enisdeasserted,therx_clk,rxd[3:0],rx_dv,rx_er,and colpinsareplacedinahigh-impedancestate. rx_encanbeusedto wireor theoutputsofmanyL80227devices inmultiportapplicationswhereonlyonedevicemaybereceivingata time,suchasinarepeaterapplication.monitoringthecrspinfrom eachindividualportenablestherepeatertoassertrx_enonlytothat L80227devicethatisreceivingdata.themethodreduces,byeightper device,thenumberofpinsandpcbtracesarepeatercoreicrequires. a.7repeaterapplications a.7.1miibasedrepeaters usingthestandardmiiastheinterfacetotherepeatercoreallowsthe L80227tobeusedasthephysicalinterfaceformiibasedrepeaters.for mostrepeaters,itisnecessarytodisabletheinternalcrsloopback. forsomeparticulartypesofrepeaters,itmaybedesirabletoeither enableordisableautonegotiation,forcehalf-duplexoperation,and enableeither100mbits/sor10mbits/soperation.settingtheappropriate bitsinthemiserialportcontrolregistercancon ? gurethesemodes. themiirequires16signalsbetweentheL80227andarepeatercore. themiisignalcounttoarepeatercoreis16multipliedbythenumberof ports,whichcanbequitelarge.thesignalcountbetweentheL80227 andarepeatercorecanbereducedbyeightperdeviceifthereceive outputpinsaresharedandtherx_enisusedtoenableonlythatport wherecrsisasserted.refertothe sectiona.6.4, receiveoutput enable, pagea-11 formoredetailsaboutrx_en. a.7.2clocks normally,transmitdataoverthemiiisclockedintotheL80227with edgesfromthetx_clkoutputclock.itmaybedesirableornecessary insomerepeaterapplicationstoclockinthetransmitdatafromamaster a-12applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. clockfromtherepeatercore.thisrequiresthattransmitdatabeclocked inonedgesofaninputclock.theoscininputclockisavailablefor clockingindataontxd.noticefromthetimingdiagramsthatoscin generatestx_clk,andtxddataisclockedinontx_clkedges.this meansthattxddataisalsoclockedinonoscinedges.thus,an externalclockdrivingtheoscininputcanalsobeusedastheclockfor txd. a.8serialport theL80227usesanmiserialporttoaccessthedeviceregisters.any externaldevicethathasaieee802.3compliantmiinterfacecanconnect directlytotheL80227withoutanygluelogic,asshownin figurea.1 through figurea.3 . asdescribedearlier,themiserialportconsistsofsixsignals:mdc, mdio,andmda[3:0]n.however,onlytwosignals,mdcandmdio,are neededtoshiftdatainandout.mda[3:0]narenotneeded,butare providedforconvenienceonly. notethatthemda[3:0]naddressesareinvertedinsidetheL80227before goingtothemiserialportblock.thismeansthatthemdan[3:0]pins wouldhavetobepinstrappedto0b1111externallytosuccessfullymatch themiphysicaladdressof0b00000onthephyad[4:0]bitsinternally. themsboftheaddressisinternallytiedtozero. a.8.1serialportaddressing tyingthemda[3:0]npinstothedesiredvalueselectsthedeviceaddress forthemiserialport.mda[3:0]nsharethesamepinsastheled outputs,respectively,asshownin figurea.5 a.atpoweruporreset,the outputdriversare3-statedforanintervalcalledthepower-onresettime. duringthepower-onresetinterval,thevalueonthesepinsislatchedinto thedevice,inverted,andusedasthemiserialportaddress.the pled[5:2]noutputsareopen-drainwithapullupresistorandcandrive ledstiedtov dd .thepled[1:0]noutputshavebothpullupand pulldowndrivertransistorswithapullupresistor,sothepled[1:0]n outputscandriveledstiedtoeitherv dd orgnd. serialporta-13 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. ifanledistobeconnectedonanledoutput,anledandresistorare tiedtov dd asshownin figurea.4 b.tosetanaddressbithigh,the ledtov dd connectionautomaticallymakesthelatchedaddressvalue ahigh.tosetanaddressbitlow,a50k resistortogndmustbe addedasshownin figurea.4 b. ifnoledsareneededontheledoutputs,theselectionofaddresses canbedoneasshownin figurea.4 c.tosetanaddressbithigh,the pinshouldbetiedtov dd .thepinishighduringpower-onresettime andlatchesinahighaddressvalue.ifalowaddressisdesired,the ledoutputpinsshouldbetiedthrougha50k resistortognd. figurea.5serialdeviceportaddressselection led 500 pled0n a. output driver/input address correspondence mda3n mda2n mda1n mda0n b. setting address with leds high pled[3:0]n led 500 low 50k c. setting address without leds 50k pled1n pled2n pled3n pled[3:0]n pled[1:0]n tie to v dd high low a-14applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. a.9oscillator theL80227requiresa25mhzreferencefrequencyforinternalsignal generation.this25mhzreferencefrequencycanbegeneratedfroman external25mhzcrystalconnectedbetweenoscinandgndorfrom applyinganexternal25mhzclocktooscin. ifacrystaloscillatorisused,itmustbeahigh-capacitancecrystal,such astheabraconablsorabls2,anditcanbeaddedbetweenthe oscinpinandgnd,asshownin figurea.6 . figurea.6connectingtheL80227toahigh-capacitancecrystal ifanonhigh-capacitancecrystalisused,a47-pfcapacitormustbe addedbetweenthecrystalandgnd,asshownin figurea.7 . figurea.7connectingtheL80227toanonhigh-capacitance crystal thereasonforusinga47pfcapacitoristhattheresonantfrequency dependsontheloadcapacitancethecrystalsees.becausethechipload capacitanceisfairlyhigh(around30pf),acapacitorinserieswiththe crystalshiftsthefrequencybacktothedesiredvalue,addingaserial capacitorisarobustandpracticalapproachtosolvinganyfrequency offsetproblemwithoutdegradingoscillatorperformance. L80227 25 mhz oscin 47 pf L80227 25 mhz oscin leddriversa-15 copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. ifanonhigh-capacitancecrystalisused,itmusthavethecharacteristics shownin tablea.3 ,andaseriescapacitormustbeaddedasshownin figurea.7 .thecrystalmustbeplacedascloseaspossibletothe oscinandgndpinssothatparasiticsonoscinarekepttoa minimum. a.10leddrivers thepled[5:0]noutputscanalldriveledstiedtov dd asshownin figurea.1 through figurea.3 .thepled[1:0]noutputscandriveleds tiedtoeitherv dd orgnd. thepled[5:0]noutputscanalsodriveotherdigitalinputs,sotheycan alsobeusedasdigitaloutputswhosefunctioncanbeuser-de ? nedand controlledthroughthemiserialport. a.11powersupplydecoupling thereareninev dd pinsontheL80227andsevengndpins. allthev dd pinsshouldbeconnectedtogetherascloselyaspossibleto thedevicewithalargev dd plane.ifthev dd pinsvaryinpotentialby evenasmallamount,noiseandlatchupcanresult.thev dd pinsshould bekepttowithin50mvofeachother. tablea.3nonhigh-capacitancecrystalspeci ? cations parameterspec typeparallelresonant frequency25mhz 0.01% equivalentseriesresistance40 max loadcapacitance18pftypical casecapacitance7pfmaximum powerdissipation1mwmaximum a-16applicationinformation copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. allthegndpinsshouldalsobeconnectedtogetherascloselyas possibletothedevicewithalargegroundplane.ifthegndpinsvaryin potentialbyevenasmallamount,noiseandlatchupcanresult.thegnd pinsshouldbekepttowithin50mvofeachother. a0.01 C 0.1 fdecouplingcapacitorshouldbeconnectedbetweeneach v dd /gndsetascloselyaspossibletothedevicepins,preferablywithin 0.5inches.thevalueshouldbechosenbasedonwhetherthenoise fromv dd -gndishigh-orlow-frequency.aconservativeapproachwould betousetwodecouplingcapacitorsoneachv dd /gndset,one0.1 f forlow-frequencyandone0.001fforhigh-frequencynoiseonthepower supply. thev dd connectiontothetransmittransformercentertapshownin figurea.1 through figurea.3 hastobewelldecoupledtominimize common-modenoiseinjectionfromthesupplyintothetwisted-paircable. itisrecommendedthata0.01 fdecouplingcapacitorbeplaced betweenthecentertapv dd andthegndplane.thisdecoupling capacitorshouldbephysicallyplacedascloseaspossibletothe transformercentertap,preferablywithin0.5inches thepcblayoutandpowersupplydecouplingdiscussedaboveshould providesuf ? cientdecouplingtoachievethefollowingwhenmeasuredat thedevice: theresultantacnoisevoltagemeasuredacrosseachv dd /gndset shouldbelessthan100mvp-p allv dd pinsshouldbewithin50mvp-pofeachother allgndpinsshouldbewithin50mvp-pofeachother. L8022710base-t/100base-txethernetphytechnicalmanual copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. customerfeedback wewouldappreciateyourfeedbackonthisdocument.pleasecopythe followingpage,addyourcomments,andfaxittousatthenumber shown. ifappropriate,pleasealsofaxcopiesofanymarked-uppagesfromthis document. impor tant:pleaseincludeyourname,phonenumber,faxnumber,and companyaddresssothatwemaycontactyoudirectlyfor clari ? cationoradditionalinformation. thankyouforyourhelpinimprovingthequalityofourdocuments. customerfeedback copyright ? 2000,2001,2002bylsilogiccorporation.allrightsreserved. reader scomments faxyourcommentsto:lsilogiccorporation technicalpublications m/se-198 fax:408.433.4333 pleasetellushowyouratethisdocument: L8022710base-t/100base- txethernetphytechnicalmanual. placeacheckmarkintheappropri- ateblankforeachcategory. whatcouldwedotoimprovethisdocument? ifyoufounderrorsinthisdocument,pleasespecifytheerrorandpage number.ifappropriate,pleasefaxamarked-upcopyofthepage(s). pleasecompletetheinformationbelowsothatwemaycontactyou directlyforclari ? cationoradditionalinformation. excellentgoodaveragefairpoor completenessofinformation____________________ clarityofinformation____________________ easeof ? ndinginformation____________________ technicalcontent____________________ usefulnessofexamplesand illustrations ____________________ overallmanual____________________ name date telephone title company name street city, state, zip departmentmail stop fax |
Price & Availability of L80227
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |